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Context 1
... proposed 5T SRAM cell with read/write assist is shown in Fig. 3. The read/write assist including a word line suppression circuit, a pre-charging circuit, a standby start-up circuit and a voltage control circuit. Amongst them, the word line suppression circuit is to provide a voltage of the selected word line when the respective word lines are in an active state. The proposed 5T SRAM cell is formed ...
Context 2
... to the bit line BL in each column. The function of the pre-charging circuit is to pull up the bit line BL of a selected column to V DD before the read or write operation. Furthermore, the standby start-up circuit is to enable the SRAM cell to quickly switch to the standby mode, and thus effectively enhance the standby performance. Refer to Fig. 3, when the write control signal WC is at logic low, the voltage of node C will be equal to that of the inverse standby control signal /S. On the contrary, when the write control signal WC is at logic high, the voltage of node C will be equal to that of the voltage of the control signal S. Thereby, in a standby operation, to effectively ...
Context 3
... to Fig. 3, prior to the write operation is performed, the write control signal WC is at logic low, the transistor P21 is turned on and the transistor N27 is turned off. Thereby, the node C is at logic high and thus to turn on the transistors N26, as such the voltage V L1 is pulled down to the ground voltage. However, during the write operation, ...
Context 4
... to Fig. 3, prior to the standby operation is performed, the inverse standby control signal /S is at logic high and thus the transistor P41 is turned off and the transistor N41 is turned on. And then, during the standby operation, the signal /S is at logic low to turn on the transistor P41 and to turn off the transistor N21. In addition, the high ...
