Figure 10 - uploaded by Anirban Pathak
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Circuit designs of (a) SR latch along with its reversible truth table and (b) D latch along with its reversible truth table.
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A clear protocol for synthesis of sequential reversible circuits from any particular gate library has been provided. Using that protocol, reversible circuits for SR latch, D latch, JK latch and T latch are designed from NCT gate library. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matc...
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Citations
... The only cheapest quantum realization of a complete (universal) 3*3 reversible gate is Peres gate and its cost is 4. The reversible logic implementation of full circuit and other adder circuits and their minimization issues has been discussed in . It has been shown in [11] and [13] that any reversible logic realization of full adder circuit includes at least two garbage outp and one constant input. The author in [10 given a quantum cost efficient reversible full adder circuit that is realized using two 3*3 Peres gates only (shown in figure 3.1). ...
... The Peres' implemented Ful Adder with its corresponding quantum cost can be seen below: ible logic implementation of full-adder circuit and other adder circuits and their minimization issues has been discussed in . It has been shown in [11] and [13] that any reversible logic realization of full adder circuit includes at least two garbage outputs and one constant input. The author in [10][11][12][13] has given a quantum cost efficient reversible full adder circuit that is realized using two 3*3 Peres gates only (shown in figure 3.1). ...
... It has been shown in [11] and [13] that any reversible logic realization of full adder circuit includes at least two garbage outputs and one constant input. The author in [10][11][12][13] has given a quantum cost efficient reversible full adder circuit that is realized using two 3*3 Peres gates only (shown in figure 3.1). This implementation of reversible full adder circuit is also efficient in terms of gate count, garbage outputs and constant input than For this implementation, I will be using the Peres gate as it is the gate with the lower quantum cost as can be seen in the figures 3.1. ...
... The method can be also applied to permutative quantum automata that have quantum memories external to the circuit. Anindita Banerjee and Anirban Pathak [22] provided a protocol for synthesis of sequential reversible circuits from any particular gate library. The reversible circuits for SR latch, D latch, JK latch and T latch are designed from NCT gate library. ...
The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. Consequently, there is a demand for high speed processors having dedicated hardware to enhance the speed with which these multiplications and accumulations are performed. In the present conventional circuits, the multiply accumulate unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the accumulator all in a single clock cycle. On the other hand, using reversible logic the implementation of digital circuits is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, a novel reversible multiply accumulate unit is proposed. the comparison of various possible implementations of the reversible multiply accumulate unit in terms of gate count, quantum cost, constant inputs and number of garbage outputs is carried out.
... Most of the reversible logic synthesis attempts are concentrated on reversible combinational logic synthesis [10][11][12][13][14][15][16][17][18][19][20][21][22][23]. Only limited attempts have been made in the field of reversible sequential circuits [24][25][26][27][28][29][30][31][32][33]. Papers [24][25][26][27][28] present reversible design of building blocks of sequential circuits such as latches and flip-flops only and suggest that larger sequential circuits be constructed by replacing the latches and flip-flops of traditional designs by the reversible latches and flip-flops. ...
... Only limited attempts have been made in the field of reversible sequential circuits [24][25][26][27][28][29][30][31][32][33]. Papers [24][25][26][27][28] present reversible design of building blocks of sequential circuits such as latches and flip-flops only and suggest that larger sequential circuits be constructed by replacing the latches and flip-flops of traditional designs by the reversible latches and flip-flops. Paper [29] deals with self-timed (asynchronous or non-clocked) design of sequential circuits. ...
... In Section II, we present the background on reversible logic. In Section III, we discuss the previous works of reversible sequential logic of [24][25][26][27][28][29][30][31][32][33]. In Section IV, we review representing a Boolean function as positive-polarity Reed-Muller (PPRM) expression and then discuss reversible logic synthesis based on PPRM expression. ...
Reversible logic is very important in low-power circuit design and quantum computing. Though a significant number of works has been done on reversible combinational logic synthesis, only few papers have been published on reversible sequential logic synthesis and per mutative quantum automata. The reported works on reversible sequential logic discuss designs of reversible flip-flops and suggest synthesizing reversible sequential circuits by replacing the flip-flops and combinational parts of traditional sequential circuit designs by their reversible counterparts. In this paper, we discuss direct design of reversible synchronous counters based on positive polarity Reed-Muller expressions. Design results show that the direct design method is more efficient than the replacement method. The method can be also applied to per mutative quantum automata that have quantum memories external to the circuit.
