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In this paper, we come up with three secure chaos-based stream ciphers, implemented on an FPGA board, for data confidentiality and integrity. To do so, first, we performed the statistical security and hardware metrics of certain discrete chaotic map models, such as the Logistic, Skew-Tent, PWLCM, 3D-Chebyshev map, and 32-bit LFSR, which are the mai...
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Conventionally, a linear feedback shift register (LFSR) constitutes linear sets of sequences with predictable periods, which are considered vulnerable to intruders. Besides, an LFSR limits the sequences of scan-for-test patterns. This work introduces a private key, which is a collection of keywords, to program the feedback coefficients and initial...
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... PN sequences are employed to encode data, for example, in spread-spectrum applications when white-noise signals are desired for transmission. LFSR is one of the simplest methods for creating PN sequences [15] . At each clock cycle in an LFSR, the bit in the register's last cell is retrieved for output, all remaining bits are moved down one cell, and a new bit is stored in the first cell. ...
The linear feedback shift register (LFSR) and Gold codes are used in telecommunications, Global Positioning System (GPS), satellite navigation, wireless systems, and code division multiple access (CDMA) dependent channel schemes for numerous radio communication technologies Gold codes are distinguished by their capacity to provide various orthogonal sequences.•The objective of the article is to focus on the design and simulation of the LFSR-based gold code generator chip in Xilinx ISE 14.7 software with the logic synthesis in Virtex-5 field programmable gate array (FPGA) and check the switching behavior with large frequency support applicable in fast-switching optical, and wireless electronics systems.
•The methodology comprises design, functional simulation with different test inputs, and FPGA synthesis. The chip design is verified for the 10-bit seeding sequence of LFSRs to result in 1023-bit code with the frequency support of 310 MHz, and 9.285 ns delay.
•The chip design is simulated based on seed data and different tap points of LFSR registers from which the bits are considered to generate the feedback. The design is scalable and has greater potential to extend to a larger extent. The behavior of the gold code depends on the maximum length sequence, absolute cross-correlation, and size of LFSR.
... The chaotic piecewise linear one-dimensional (PL1D) map is a mathematical model that exhibits chaotic behavior in a one-dimensional space [23]. It is a type of dynamical system that evolves over discrete time steps and is characterized by a sequence of piecewise linear transformations. ...
Lightweight ciphers have been developed to meet the rising need for secure communication in environments with limited resources. These ciphers provide robust encryption while ensuring efficient computation. Our paper introduces a new enhanced PRESENT lightweight cipher that utilizes chaotic systems to enhance its robustness and randomness while retaining the simplicity and compactness of the original cipher. By integrating chaotic maps into the cipher's core components, we improve its resistance against advanced cryptanalysis, such as differential, Salt and Peppers Noise (SPN), and loss data attacks. We also optimize the design for computational efficiency, making it suitable for deployment in devices with limited resources. Through extensive simulations and comparative analyses, we demonstrate the superiority of our enhanced cipher in terms of security and efficiency compared to other state-of-the-art lightweight ciphers. Our research contributes to the advancement of lightweight cryptography and provides a promising solution for secure communication in resource-constrained environments.
... FPGAs have also been used to implement memory-based systems, as shown in [7], where the authors show an encryption application and FPGA realization of a fractional memristive chaotic system. More elaborated applications can also be found in recent works, such as that described in [8], in which the design, hardware implementation and performance analysis of three chaos-based stream ciphers using FPGAs are presented. This study also emphasizes the generation of robust pseudo-random number generators of chaotic sequences and their corresponding stream ciphers. ...
Mechanical jerk systems have applications in several areas, such as oscillators, microcontrollers, circuits, memristors, encryption, etc. This research manuscript reports a new 3-D chaotic jerk system with two unstable balance points. It is shown that the proposed mechanical jerk system exhibits multistability with coexisting chaotic attractors for the same set of system constants but for different initial states. A bifurcation analysis of the proposed mechanical jerk system is presented to highlight the special properties of the system with respect to the variation of system constants. A field-programmable gate array (FPGA) implementation of the proposed mechanical jerk system is given by synthesizing the discrete equations that are obtained by applying one-step numerical methods. The hardware resources are reduced by performing pipeline operations, and, finally, the paper concludes that the experimental results of the proposed mechanical jerk system using FPGA-based design show good agreement with the MATLAB simulations of the same system.
... FPGAs have also been used to implement memory-based systems, as shown in [7], where the authors show an encryption application and FPGA realization of a fractional memristive chaotic system. More elaborated applications can also be found in recent works, such as that described in [8], in which the design, hardware implementation and performance analysis of three chaos-based stream ciphers using FPGAs are presented. This study also emphasizes the generation of robust pseudo-random number generators of chaotic sequences and their corresponding stream ciphers. ...
... In the last few years, many investigations have been performed on chaos-based image encryption and secure communication systems. Examples can be found in [31][32][33][34][35][36][37][38][39], which are all implemented on the field programmable gate array (FPGA) cards. For electronic implementations, the FPGA has become a better choice over operational amplifiers (OPAMPs) because it is reusable, very cost-effective, faster in performing parallel processing, and faster and efficient with regard to system design. ...
The main objective of this work was to implement the parameter-switching chaos control scheme for fractional-order spherical systems and develop a chaos-based image encryption and transmission system. The novelty in the developed secure communication system is the application of the parameter-switching scheme in the decryption of RGB and grayscale images, which undergo one round of encryption using the chaotic states of the fractional system and a diffusion process. The secure communication system has a synchronized master and slave topology, resulting in transmitter and receiver systems for encrypting and decrypting images, respectively. This work was demonstrated numerically and also implemented on two FPGAs, namely Artix-7 AC701 and Cyclone V. The results show that the parameter-switching scheme controls chaos in the fractional-order spherical systems effectively. Furthermore, the performance analysis of the image encryption and transmission system shows that there is no similarity between the original and encrypted images, while the decryption of the encrypted images is without a loss of quality. The best result in terms of the encryption was obtained from the chaotic state x of the fractional-order system, with correlation coefficients of 0.0511 and 0.0392 for the RGB and grayscale images, respectively. Finally, the utilization of the FPGA logical resources shows that the implementation on Artix-7 AC701 is more logic-efficient than on Cyclone V.
... Chaos theory relates the chaotic dynamics of systems with initial conditions and unstable periodic motions [42]. It is applied in various applications such as biometric security [43], embedded systems [44], communications [45], lasers [46], pumped storage units [47], The third domain is evolutionary techniques applied to optimization problems. In differential evolution [30], an optimization solution is obtained by using mutation, crossover, and selection operators. ...
... Chaos theory relates the chaotic dynamics of systems with initial conditions and unstable periodic motions [42]. It is applied in various applications such as biometric security [43], embedded systems [44], communications [45], lasers [46], pumped storage units [47], encryption systems [48], the Internet of Things [49], image processing [50], and image encryption [51]. ...
In this article, a chaotic computing paradigm is investigated for the parameter estimation of the autoregressive exogenous (ARX) model by exploiting the optimization knacks of an improved chaotic grey wolf optimizer (ICGWO). The identification problem is formulated by defining a mean square error-based fitness function between true and estimated responses of the ARX system. The decision parameters of the ARX model are calculated by ICGWO for various populations, generations, and noise levels. The comparative performance analyses with standard counterparts indicate the worth of the ICGWO for ARX model identification, while the statistical analyses endorse the efficacy of the proposed chaotic scheme in terms of accuracy, robustness, and reliability.
