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Simple, physics-based MOSFET noise models, valid over the linear, saturation, and subthreshold operation regions are presented. The consistency of the models representing series-parallel associations of transistors is verified. Simple formulas for hand analysis using the inversion level concept are developed. The proportionality between the flicker...
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... Fig. 6, we present the simulated and measured corner fre- quency of a saturated NMOS transistor for various bias currents. The solid line represents calculated using (22) together with the measured value for . The dashed line represents cal- culated using expression (13) for . For this transistor, the dimensionless factor . Both simu- lations ...
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Silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are excellent candidates to become an alternative to conventional bulk technologies. The most promising SOI devices for the nanoscale range are based on multiple gate structures such as double-gate (DG) MOSFETs. These devices could be used for high-frequency app...
Citations
... The 1pF capacitor of the PTAT receiver 225 shown in Figure 5 (b) shunts the noise generated by the transistor N 3 to the ground. We will assume that the input referred noise will be dominated by only the thermal noise [26,27], even though the effect of flicker-noise could also be incorporated [28,29]. ...
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Portable and embedded ultrasound applications require energy-efficient receivers that can operate over a wide range of incident ultrasonic energy. In this paper we show that by directly injecting the ultrasonic signal into a proportional-to-absolute-temperature (PTAT) reference circuit, the pre-amplification and rectification stages used in a conventional ultrasonic receiver can be eliminated which leads to a significant improvement in the system energy-efficiency. The PTAT circuit self-biases itself in accordance to the magnitude of the incident ultrasound pressure signal and is also configured to function as an active diode (with threshold voltage of ≈25 mV) to achieve signal rectification. In this paper we present measurement results obtained from a PTAT-based ultrasound receiver that has been prototyped in a 0.5 μm CMOS process, and we compare the performance to a standard transconductance amplifier (TCA) based design that has also been prototyped in the same process. The improvement in input dynamic range was measured to be 25 dB and sensitivity of the PTAT-based receiver was measured to be 21 Hz/mV when the biasing current is 16.67 nA. We also present the bit-error-rate (BER) performance when the receiver circuit is used for a substrate communications application where ultrasound is used for transmitting and receiving data through an Aircraft grade Aluminum plate.
... According to [4], [5], the power-spectral density (PSD) of the current noise, for saturated transistors in weak inversion, is given by ...
In view of the ultra-low-power (ULP) consumption that is often demanded in internet-of-things (IoT) applications, several CMOS voltage reference circuits have been reported consuming from picowatt down to femtowatt powers. Such ULP performance is achieved by biasing transistors using extremely low currents. In this way, the lower is the bias current the higher the intrinsic thermal noise is, and its influence on the design cannot be neglected. In this paper, analytical expressions for both thermal and flicker noises for 3-transistor (3T) voltage references are advanced in order to quantify the intrinsic noise influence on the circuit performance. The results were validated by extensive simulations with HSPICE using a 180 nm CMOS process.
... Because of the extremely low amplitude of the input signal (tens of lV), and the ultra-low power consumption specified for implantable electronics, the design of electroneuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. Flicker noise can be reduced using large input transistors, or chopper amplifiers [1][2][3], but it is necessary to increase the supply current (I DD ) to reduce thermal noise [1]. Because the thermal noise is related to I DD but not necessarily to power, stateof-the-art low-power low-noise amplifiers tend to use a low supply voltage [4][5][6]. ...
... Because of the extremely low amplitude of the input signal (tens of lV), and the ultra-low power consumption specified for implantable electronics, the design of electroneuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. Flicker noise can be reduced using large input transistors, or chopper amplifiers [1][2][3], but it is necessary to increase the supply current (I DD ) to reduce thermal noise [1]. Because the thermal noise is related to I DD but not necessarily to power, stateof-the-art low-power low-noise amplifiers tend to use a low supply voltage [4][5][6]. ...
... The former depends on the total area of the transistors and eventually can be reduced to a negligible value by means of circuit techniques like chopper and autozero. But thermal noise depends on the DC bias current of the transistors and it is only possible to reduce it by increasing the current and thus power consumption [1]. The thermal noise current power spectrum density (PSD) S Ith (f), and flicker noise current PSD S I1/f (f), of a single transistor can be expressed: ...
Noise Efficiency Factor (NEF) is the most employed figure of merit to compare different low-noise biomedical signal amplifiers, taking into account current consumption, noise, or bandwidth trade-offs. A small NEF means a more efficient amplifier, and was assumed to be always NEF > 1 (an ideally efficient single BJT amplifier). In this work current-reuse technique will be utilized to exceed this limit in a very efficient CMOS amplifier. A micro-power, ultra-low-noise amplifier, aimed at electro-neuro-graph signal recording in a specific single-channel implantable medical device, is presented. The circuit is powered with a standard medical grade 3.6 V(nom) secondary battery. The amplifier input stage stacks twelve differential pairs to maximize current-reuse. The differential pair stacking technique is very efficient: allows most of the energy to be dissipated in the input transistors that amplify and not in mirror or bias transistors, and allows also the input transistors to operate with a reduced VDS just above saturation. The amplifier was implemented in a 0.6 μm technology, it has a total gain of almost 80 dB, with a 4 kHz bandwidth. The measured input referred noise is 4.5 nV/Hz1/2@1 kHz, and 330 nVrms in the band of interest, with a total current consumption of only 16.5 μA from the battery (including all the 4 stages and the auxiliary circuits). The measured NEF is only 0.84, below the classic NEF = 1 limit.
... where q is the charge of the electron, W, L, and C ′ ox are the length, width, and capacity per unit area of the transistor, respectively, and N ot is the effective number of traps. 12 As can be seen from Equations 4 to 6 because of the similarity of the PSDs, the transistors should operate at the same inversion level as determined by the thermal noise analysis. The only difference between flicker and thermal noise is that none of the transistors of the output stage of the potentiostat are multiplied by 1/A, so they all have equal weight in the contribution of noise. ...
... In this section we use the Hajimiri-Lee model of the phase noise in oscillators [4,5], together with the MOSFET noise model described in [7], to evaluate the phase noise of the ESCO. ...
... where , the so called noise excess factor, is a function of the inversion level [7,8], ...
... The 1⁄ noise power spectral density is given by [7] ,1/ = ...
This paper presents an analysis of the phase noise in Enhanced Swing Colpitts Oscillators with transistor operating in moderate inversion. The analyzed oscillator was designed to operate around 2.1 GHz. The phase noise analysis is based on the Impulse Sensitivity Function-ISF, and considers the transistor's flicker and thermal noise contributions as functions of the inversion level.
... where Sv ' is the PSD of the flicker noise voltage for each transistor M ' and according to [1], it can be derived as ...
This work presents a computer-aided design (CAD) approach for voltage reference circuits by controlling main characteristics, such as temperature coefficient, power consumption, mismatch caused by the manufacturing process, transistor area and output noise. The CAD tool and the proposed methodology allow the designer to obtain accurate and optimum initial circuit sizing, thereby reducing the large number of computer runs usually required in voltage reference circuit designs. An illustrative example was carried out in a 180 nm CMOS process and verified by post layout simulations, whose results were in close agreement with the tool predictions, as shown in this paper. The reference circuit achieves an output voltage of 500 mV, a temperature coefficient of 15.19 ppm/∘C over the temperature range of -40∘C to 100∘ C, a maximum quiescent current of 5 uA, a power supply rejection ratio of -57 dB, and a line regulation of 0.250 % from 1.2 V to 1.8 V supply voltage. The chip occupies an area of 0.072 mm2 .
... It is quite well accepted that in the MOS transistor, the sources of flicker noise (or 1/f noise) are mainly correlated carrier number and mobility fluctuations, due to the random trapping-detrapping of carriers in energy states named 'traps' inside the oxide near the surface of the semiconductor [1][2]. In transistors with very small dimensions the effect of a single or few discrete traps in the noise power spectral density (PSD) can be observed [3]. ...
... has been widely adopted by the designers, because it is very appropriate for hand and approximated numerical calculations [1,4,5]. Moreover Eq. (1) has been demonstrated in [1] as a good approximation of a physical model shown in (2). ...
... has been widely adopted by the designers, because it is very appropriate for hand and approximated numerical calculations [1,4,5]. Moreover Eq. (1) has been demonstrated in [1] as a good approximation of a physical model shown in (2). In (1) S Id is the noise current PSD of a transistor, K F , EF, are constants to adjust, C 0 ox is the oxide capacitance per unit area, g m , W, L, are the transistor transconductance, width, and length respectively. ...
In this work, a consistent, physics-based, one-equation-all-regions model for flicker noise in MOS transistors that considers both mobility and carrier number fluctuations is presented. The final result resembles the known BSIM flicker noise model, but some inconsistencies are avoided because approximations and interpolation are not necessary. Exact noise integration along the channel was possible with the aid of a one-equation-all-regions dc model of the MOS transistor. Finally a brief discussion based on SPICE noise simulations and some noise measurements is presented, about which of the terms of the new model are necessary for the designer, that require accurate but simple equations for the design space exploration.
... The mean of the applied noise, and thus of its components, is zero [34]. Flicker noise (also known as 1/f noise or pink noise) is a yet not fully understood phenomenon and a subject of much controversy [1]. One widely accepted explanation is based on trap-assisted recombination. ...
Current CMOS (Complementary Metal Oxide Semiconductor) technologies show an increasing susceptibility to a rising amount of failure sources. This includes also radiation induced soft errors, which requires countermeasures on several design levels. Hereby, BBICS (Bulk Built-In Current Sensors) represent a promising approach on circuit level. However, it is expected that these circuits, like similar sensors measuring substrate effects, are strongly susceptible to substrate noise. The intention of this work is an in-depth noise analysis of representative bulk sensors based on extracted layout data. Thereby, several aspects are considered, like sensor activation thresholds, impact of the distance to the noise source, and noise generation by test circuits. Results indicate that already noise RMS level of 5 to 9 % of the supply voltage can lead to false detections, which are values in the same order of magnitude of noise generated by test circuits.
... where Sv ' is the PSD of the flicker noise voltage for each transistor M ' and according to [1], it can be derived as ...
This work presents a computer-aided design (CAD) approach for voltage reference circuits by controlling main characteristics of voltage references, such as temperature coefficient, power consumption, mismatch due to the manufacturing process, transistor area, and output noise. The CAD tool and the proposed methodology allow the designer to obtain accurate and optimum initial circuit sizing, thereby reducing the large number of computer runs usually required in voltage reference circuit designs. Shown in this paper, an illustrative design example was carried out in a 180nm CMOS process and verified by post layout simulations, whose results were in close agreement with the CAD tool predictions.
... Using equations (2) and (3), together with the ACM MOSFET model equations, the de sign of the first stage was done to obtain a noise level below 244 /-lVRlvIs, keeping a compromise between area and en ergy consumption. The simplified model parameters of the thermal and flicker noise used in (2) and (3) were extracted through simulations using the BSIM4 transistor model, pro viding consistent results with series-parallel associations of transistors [21] required when large transistors are laid out as multi-finger fractured transistors. The noise calculated for the output of the pre-amplifier was 161 /-lV RMS. ...
This paper presents a high-linearity and large output swing instrumentation amplifier for portable multichannel biomedical applications. It is composed of a fully differential two- stage CMOS amplifier in which a feedback provides stable signal gain that can be adjusted from 25 to 100 V/V. Additionally, a pseudo-resistive feedback combined with an appropriate input capacitive coupling provides a high-pass behavior, presenting a -3 dB cut-off frequency lower than 120 mHz. The amplifier is fully integrated in a 130 nm CMOS process, using only 0.1 mm2 of silicon area, including large matched capacitor banks. Its power consumption is 31.3 μW under a 1.5 V supply. The pre-amplifier gain reaches less than 0.02 % of THD (total harmonic distortion) for an output swing of 2 Vpp in post-layout simulations. The total input-referred noise estimated from simulations is 1.93 μVrms inside the 0.5 Hz to 500 Hz frequency range.
