Fig 13 - uploaded by Akash Levy
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CGRA with processing element (PE) and memory (MEM) tiles and a configurable interconnect. Also shown are the multiplexers in the switch box (SB) and connection box (CB) that we replace with NEMS-based variants.
Source publication
![Fig. 4. Area utilization of the NEM relay in [8] (left) versus this...](profile/Akash-Levy-2/publication/364557676/figure/fig3/AS:11431281092088132@1666704860815/Area-utilization-of-the-NEM-relay-in-8-left-versus-this-work-right_Q320.jpg)
We propose the use of multi-pole nanoelectromechanical (NEM) relays for routing multi-bit signals within a coarse-grained reconfigurable array (CGRA). We describe a CMOS-compatible multi-pole relay design that can be integrated in 3-D and improves area utilization by 40% over a prior design. We then demonstrate a method for placing multiple contact...
Citations
... The rest of this chapter is adapted from our published paper [61]. We extend prior work, by ...
... showing that integration of multi-pole NEM relays into a place-and-routed CGRA design improves PPA, thereby reducing reconfigurability overhead [60,61]. The major contributions of this chapter are: ...
In this dissertation, I present techniques for improving the power, performance, and area of integrated circuits (ICs) through 3-D integration of two emerging nanotechnologies: (1) resistive random-access memory (RRAM), a non-volatile memory with multiple-bits-per-cell storage capability, and (2) nanoelectromechanical (NEM) relays, nano-scale mechanical relays that can be actuated electrostatically. In modern ICs for edge computing, data movement between on and off-chip memories typically consumes a large fraction of the total power. Dense, non-volatile embedded memory can reduce/eliminate off-chip data movement by keeping frequently-read application data always on chip. RRAM is a good candidate for such a memory, especially because it can store multiple bits per cell, achieving high density on-chip storage. However, efficient and reliable operation with multiple-bits-per-cell RRAM has been a challenge due to (1) stochastic device behavior during programming that results in large pulse counts with traditional write-verify methods, and (2) reliability issues arising from resistance relaxation. Towards the goal of achieving efficient and reliable multiple-bits-per-cell RRAM, I present three contributions: (1) range-dependent adaptive resistance (RADAR) tuning, a fast and energy-efficient programming method for multiple-bits-per-cell RRAM that uses an adaptive combination of coarse- and fine-grained cell resistance tuning, yielding a 2.4x reduction in pulse count over prior methods, (2) characterization of resistance relaxation behavior in three RRAM technologies and analysis of its implications for multiple-bits-per-cell storage, and (3) efficient multiple-bits-per-cell embedded RRAM (EMBER), the first demonstration of a fully-integrated multiple-bits-per-cell RRAM macro. EMBER contains a multiple-bits-per-cell read and write controller with a high degree of flexibility that enables good level allocation (mitigating reliability issues from resistance relaxation) and programming scheme optimization (yielding low-energy, low-latency multiple-bits-per-cell writes). Finally, in reconfigurable ICs, in addition to the memories, the routing fabric consumes a large fraction of the overall area and power. I demonstrate that replacing CMOS routing switches with 3-D integrated multi-pole nanoelectromechanical (NEM) relays in a coarse-grained reconfigurable array (CGRA) can achieve 19% lower area and 10% lower power at iso-performance.
