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This article unveils a new hybrid configuration of ring type VCO (voltage controlled oscillator) consisting of CMOS and current starved inverter to generate full voltage swing. A certain number of such inverters are cascaded alternatively to obtain the output frequency (fosc). The novelty lies in the fact that this design offers a good trade-off of...
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Context 1
... ring oscillator (RO), formed as a cascaded delay cells is of two types: single ended RO and differential RO. In both approaches, the delay of each stage is controlled by control voltage (V c ), which is shown in Fig. 1 ...
Context 2
... reason of obtaining wide FTR is explained with the following setup shown in Fig. 10, which shows a small-signal model of current starved inverter ...
Context 3
... To understand the modulation of R ON4 and R ON5 , a test setup is carried out with 7-stage CS-CMOS inverter chain and 7-stage CS-inverter chain and both are driven by an input pulse of 50 MHz with rise time and fall time of 10 ps each. Under this condition, the transient at all the 7 nodes (Y1 to Y7) are noted for both the networks as shown in Fig. ...
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Citations
... A novel ring oscillator topology is designed by Li et al. [9] measures high frequency of oscillation and high tuning range but consumes high power. Maiti et al. [10] developed a hybrid power efficient ring VCO giving penalty of lower frequency of oscillation and low tuning range. In [11] authors developed a ring oscillator based on the current source this design consumes less power but lacks in frequency tuning. ...
... x phl1 and x plh1 is the delay for high to low and low to high transition respectively. During high to low transition x 2 − x 1 and x 3 − x 2 is expressed in (9) and (10). By adding (9) and (10) high to low and low to high transition delay expressed in (12) and (13) respectively. ...
p> The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal–oxide–semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation. </p
... As a result, these resistors are implemented off-chip. Furthermore, integrated resistors are sensitive to process, voltage, and temperature fluctuations [30], so implementing the resistors off-chip increases the circuit's robustness to PVT variations. Fig. 11a represents the output signal for several values of the input charge following each other at different frequencies of appearance. ...
... Indeed, a circuit must be able to work over the variations of the parameters such as voltage, process, and temperature. Post-layout Monte-Carlo simulation has been performed to verify the reliability and the sturdiness of the proposed design [30,33]. It consists in our case in randomly varying the surface of the tran-sistor channel, which could occur during lithography, between two values, nominal value +/-tolerance. ...
In this study, a time-variant baseline restorer (TV-BLR) circuit was designed and implemented to address the poor frequency selectivity issue in the shaping units of most state-of-the-art readout electronics for CdZnTe/CdTe detectors used in biomedical imaging applications. The proposed circuit improves image quality by canceling the artifacts that result from poor temporal and energy resolution in PET imaging. The proposed circuit consists of a Charge Sensitive Preamplifier (CSP) followed by a classical pole-zero compensation circuit. Two stages of integrators are added and a frequency rectifier module named the TV-BLR circuit has been built. The open-loop amplifier for the CSP is a single-ended input stage amplifier, designed for low-power applications with a maximum power consumption of 43 µW from a 1.2 V supply voltage, verified through post-layout Monte Carlo simulations. The TV-BLR increases the selectivity of the shaping filter, lowers the equivalent noise charge (ENC), and restores the baseline of the circuit to only 143 µV dc-offset. It also extends the counting rate behavior of the system by handling the time-over-threshold (ToT), which depends on the tail current (Itail) of the comparator stage. The circuit was designed, simulated, and validated for an input dynamic of 2–12.5fC, providing an energy range of 55.1–354.3 keV. The design has a charge-to-voltage conversion factor of 56.7 mV/fC with a 4% non-linearity error for an input detector capacitance of 200 fF, while achieving an optimal ENC of 57.4 e − RMS ± 0.1 e−/fC with 13.27 ns peaking time. Process Voltage Temperature (PVT) analysis was performed to validate the simulation results and performance metrics of the design. The proposed design improves energy resolution and avoids energy losses due to the readout system.
... Fig. 5 shows the post-layout simulation results of the designed RO's phase noise. The figure of merit [FOM, defined in [16] and copied in (7)] of this design is -169 dBc/Hz by calculation and -163 dBc/Hz from simulation with the value of p avg (power dissipated in mW of the ring oscillator) to be 5.4 μW. Thanks to the dynamic body biasing scheme, this FoM sits at the highend of typical RO designs, which ranges from -120 dBc/Hz to -170 dBc/Hz for various ROs summarized in [17]. ...
Passive radio-frequency identification (RFID) tags,
when placed remotely or in harsh environments, will benefit
the most if the communication distance between the tag and
reader is vastly improved. The bistatic backscattering technique
provides a solution to this problem by separating the carrier
and backscattered signal in frequency, which helps mitigate
interference. It also decouples the reader from carrier generation
by having a separate radio-frequency (RF) emitter and further
improves the signal strength by reducing round trip path loss.
A dual-band on-chip bistatic backscattering circuit design for
passive RFID tags is presented in this paper using a 180
nm CMOS process dissipating 35 μW of power. Post layout
simulation results provide a communicable distance of 170 m
between the tag and reader at 868 MHz and 60 m at 2.4 GHz
when the tag is kept 5 m away from the RF emitter.
... Here we address how such heterogeneities affect the synchronization properties of such systems. Apart from component heterogeneity, the complexity introduced by time-delayed coupling, noise, and environmental effects (PVT variations) pose additional challenges to the reliable operation of these devices [20][21][22][23]. Time delay, for example, has significant effects on the collective dynamics, especially when the systems are operating at high frequencies and/or involved in long-range signal transmissions [24][25][26][27]. ...
We study synchronization in networks of delay-coupled electronic oscillators, so-called phase-locked loops (PLLs). Using a phase-model description, we study the collective dynamics of mutually coupled PLLs and report the phenomenon of heterogeneity-induced synchronization. This phenomenon refers to the observation that heterogeneity in the system's parameters can induce synchronization by stabilizing the states which are unstable without such heterogeneity. In systems where component heterogeneity can be tuned and controlled, we show how the complex collective self-organized dynamics can be guided towards synchronized states with specific operational frequencies and phase relations. This is of importance for the technical applicability of self-organized dynamics. In electrical engineering, for example, where components can be strongly heterogeneous, our theoretical framework can inform the design process for networks of spatially distributed PLLs. The results presented here are also useful in understanding the collective dynamics in ensembles of phase oscillators with time-delayed interactions, inertia, and heterogeneity.
A real-time temperature-adaptive phase-locked loop (PLL) is proposed in this brief. To prevent the PLL from going out of lock due to significant temperature variation, a temperature-compensated loop based on the idle circuits of automatic amplitude control (AAC) is designed, which senses temperature variation by detecting the changes of output amplitude. The PLL output frequency is then adjusted by controlling the temperature-compensated varactor of the voltage-controlled oscillator. The proposed PLL is fabricated in a 22 nm silicon on insulator (SOI) process, which covers 0.27 mm2 of the chip area. The temperature-compensated loop dissipates only 40 uA under 0.9 V supply voltage while the overall PLL consumption is 10 mA. The tuning voltage of VCO can be controlled within 200 mV, while PLL maintains locked in the ambient temperature range from −40 °C to 170 °C.
Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage-controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high-performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap-gate transistors, this work aims to propose a carbon nanotube field-effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10-nm gate-all-around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA-CNTFET-based ring VCO consumes 85.176 μW at (Formula presented.) with a 6.12- to 10.42-GHz frequency tuning range. At the worst-case noise conditions, the proposed design presents -90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA-CNTFET-based VCO can be considered as a potential candidate for X-band satellite communication applications.
A wide tuning range, low phase noise oscillator with 3 stage differential configuration is presented. GPDK 45 nm CMOS Technology is selected for the design and simulation of the proposed circuit, under power supply impediment of 1.1 V. Proposed delay cell features ultra wide tuning range as it utilizes dual control voltages (Vc1 and Vc2), enabling large current to flow in the circuit. As frequency of oscillation has linear proportionality with the bias current, this oscillator generates frequencies from 534 MHz to 18.56 GHz. The proposed circuit occupies chip area of 102.87μ m2. This circuit offers power consumption of 1.13 mWatt and phase noise of −108.61dBc/Hz (10 MHz offset frequency) at 5.82 GHz oscillation frequency. Performance of the proposed circuit is evaluated on various temperature, supply voltage and process corners. Total Harmonic Distortion (THD) profile is also measured through simulation. Because of wide frequency spectrum, low phase noise, small area and low power budget, proposed circuit can be utilized in various power electronic applications, medical equipments, communication and navigation systems.
