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The paper describes a signed digit full adder (SDFA) circuit
consisting of resonant tunneling diodes (RTDs) and metal oxide
semiconductor field effect transistors (MOSFETs). The design is
primarily based on a multiple valued logic literal circuit that utilizes
the folded back I-V (or negative differential resistance, NDR)
characteristics of RTDs to...
Contexts in source publication
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... devices are very useful in a current-mode logic with wired-summation of digits that saves circuit area. Second, the folded I-V characteristic of the RTD can be utilized to build high functionality literal gates which can be put to- gether to form multiple-valued logic adders, enabling the ensuing RTD-based adder design to be even more compact. Fig. 1 depicts a block diagram of the signed-digit addition approach proposed in this work. Lines x i , y i , c i , w i , and s i are three-valued, current-mode signals. Addition of x i and y i is achieved by simple wired-summation of currents. The function of the SDFA block is to convert the summation of input signal, z, to a two-digit ...
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... equation is solved using the initial condition V node (0) = V za -V p , which yields Fig. 10 shows the graph obtained for the given RTD characteristics using the method described. The experiments showed that t b is always very small because the transient of V node in the NDR region is very sharp. Therefore, the delay time is predomi- nantly determined by the time, t a , taken to reach I I R p s = ...
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... criteria for selecting R s is a trade-off between the delay and the input resistance of the literal circuit. While it is necessary to minimize the delay of the configuration, it is also necessary to maximize the input resistance. The high- est value of R s such that the delay is not sharply increased is then selected (Fig. 10). Using this criteria and the graph, R s 35 ohms is considered a reasonable value. Please note that the input resistance of the literal circuit is given by the sum of R s and the positive resistance of the ...
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... was verified using NDR-SPICE [25], [26], [27]. This circuit simulation tool includes SPICE models for RTDs and other NDR devices. The simulator also makes use of special convergence routines that elimi- nate false oscillations and other convergence problems that arise when simulating NDR-based circuits with conven- tional circuit simulators. Fig. 11a shows a transient analysis output trace obtained from a simulation of the SDFA circuit. This simulation experiment includes both cases for ...
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... signal has fast transients in order to avoid contribution of the input signal rise and fall times to the delay measured at the output. In the second experiment, the input signal V z is stepped through its different logic levels, which were de- termined in the first experiment. The simulation traces ob- tained in the second experiment are shown in Fig. 11b. These traces show a good matching of circuit operation with respect to the desired SDFA functions shown in Fig. 2. Table 2 summarizes the results of the measurements for both simulation experiments. The noise margin was meas- ured in the first experiment with respect to the least wide pulse in output signal w (as shown in Fig. 11a). ...
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... are shown in Fig. 11b. These traces show a good matching of circuit operation with respect to the desired SDFA functions shown in Fig. 2. Table 2 summarizes the results of the measurements for both simulation experiments. The noise margin was meas- ured in the first experiment with respect to the least wide pulse in output signal w (as shown in Fig. 11a). The levels i a and i b of input signal V z at 50 percent of each transition of the selected pulse of w are measured. The noise margin is obtained by assuming that the operating point is at the middle of the selected output pulse. Hence, the noise mar- gin is half of the difference between the measured current values of signal V z , ...
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... The noise margin is obtained by assuming that the operating point is at the middle of the selected output pulse. Hence, the noise mar- gin is half of the difference between the measured current values of signal V z , that is, NM = |i a -i b |/2. The value of power dissipation given in Table 2 was obtained in the sec- ond simulation experiment (Fig. 11b). The frequency of op- eration affects the value of the measured power dissipation. Finally, the delay of the circuit was measured as the time elapsed between 50 percent of the transition in the input signal, V z , and 50 percent of the resulting transition in the output signal (in the second experiment). Both rising and falling delays ...
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... the SDFA prototype, it was necessary to modify the implementation as follows. The modification consisted of replacing the inverter of all the literal circuits by a voltage comparator, as shown in Fig. 12a. Fig. 12b shows the com- parator circuit used in the SDFA prototype. This is not the most compact option for solving the problem, but it is the most flexible. Instead of altering the threshold voltage of the inverter by using circuit techniques, such as replacing the PMOS transistor of the inverter by a resistive load, the design allows for the ...
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... types of devices. If a w current generator using only PMOS devices was required, it would then be neces- sary to insert two inverters in the SDFA circuit to generate the complements of literal signals lit1 and lit2. In the test chip, one of the SDFA cell prototypes was built using this approach. The microphotograph of the chip is shown in Fig. 13b. Fig. 13a shows a microphotograph of the simple SDFA cell which requires a reduced number of transistors by us- ing the interim sum current generator which combines NMOS and PMOS transistors. In both versions of the pro- totype, inverters were replaced by voltage comparators, as described in the previous ...
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... of devices. If a w current generator using only PMOS devices was required, it would then be neces- sary to insert two inverters in the SDFA circuit to generate the complements of literal signals lit1 and lit2. In the test chip, one of the SDFA cell prototypes was built using this approach. The microphotograph of the chip is shown in Fig. 13b. Fig. 13a shows a microphotograph of the simple SDFA cell which requires a reduced number of transistors by us- ing the interim sum current generator which combines NMOS and PMOS transistors. In both versions of the pro- totype, inverters were replaced by voltage comparators, as described in the previous ...
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... of the prototype is to demonstrate the functionality of the SDFA cell, an experiment to show the transfer characteristics of the circuit was performed. These transfer characteristics were obtained by feeding the input of the circuit with a ramp signal of very low slew-rate. The ex- periment was done using the second version of the SDFA cell (Fig. 13b). The oscilloscope traces obtained in the experiment are shown in Fig. 14. In general, the form of the measured output functions agree with the expected circuit behavior shown in Fig. 11. Please note that the experiment is divided into two parts with respect to the value of V values. While the expected output currents for logic levels ...
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... an experiment to show the transfer characteristics of the circuit was performed. These transfer characteristics were obtained by feeding the input of the circuit with a ramp signal of very low slew-rate. The ex- periment was done using the second version of the SDFA cell (Fig. 13b). The oscilloscope traces obtained in the experiment are shown in Fig. 14. In general, the form of the measured output functions agree with the expected circuit behavior shown in Fig. 11. Please note that the experiment is divided into two parts with respect to the value of V values. While the expected output currents for logic levels "-1," "0," and "1" are 0.0, 0.5, and 1.0 milliampere, respec- tively, the ...
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... were obtained by feeding the input of the circuit with a ramp signal of very low slew-rate. The ex- periment was done using the second version of the SDFA cell (Fig. 13b). The oscilloscope traces obtained in the experiment are shown in Fig. 14. In general, the form of the measured output functions agree with the expected circuit behavior shown in Fig. 11. Please note that the experiment is divided into two parts with respect to the value of V values. While the expected output currents for logic levels "-1," "0," and "1" are 0.0, 0.5, and 1.0 milliampere, respec- tively, the measured current levels are 0.0, 0.2, and 0.4 milli- ampere (Fig. 14). This alteration of the current levels is ...
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... agree with the expected circuit behavior shown in Fig. 11. Please note that the experiment is divided into two parts with respect to the value of V values. While the expected output currents for logic levels "-1," "0," and "1" are 0.0, 0.5, and 1.0 milliampere, respec- tively, the measured current levels are 0.0, 0.2, and 0.4 milli- ampere (Fig. 14). This alteration of the current levels is due, in part, to a reduction in the transconductance of the PMOS devices-from 20.563 mA/V 2 in the SPICE model used for the simulations, to 16.129 mA/V 2 measured for the actual CMOS run of the test chips. Another reason for the difference in output levels is due to the method used for ...
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... Combinational and sequential logic circuits such as multiplexer, decoder, full adders, D flip-flop, and shift registers using NDR devices have also been demonstrated (Prost et al., 1998;Mazumder et al., 1998;Gonzalez and Mazumder, 1998). ...
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FPGA structures are widely used due to early time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of signals in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In this work we propose a new FPGA structure based on a low-power quaternary voltage-mode device. The most important characteristics of the proposed architecture are the reduced fanout, low number of wires and switches, and the small wire length. We use a set of FIR filters as a demonstrator of the benefits of the quaternary representation in FPGAs. Results show a significant reduction on power consumption with small timing penalties.
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