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Block diagram of the developed system. In this approach a structuring element representing an object shape is decomposed along the pipeline architecture.
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Mathematical morphology supplies powerful tools for low level image analysis, with applications in many areas. In this paper, the development of a novel reconfigurable hardware using a genetic algorithm and a pipeline architecture is proposed for the task of shape recognition in binary images. For the recognition process, a large sized convex struc...
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... block diagram of the developed system is shown in Fig. 1. A genetic procedure, developed using Matlab, decomposes a convex structuring element into a linear chromosome. This chromosome is then used to configure each stage of the pipeline architecture. Each stage from the architecture can handle a 3x3 sized structuring element. A configuration file that contains the structuring element shape ...
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... Fig. 10 an original image containing three objects of different shapes is presented. The goal in this case was to verify the presence of the middle object. An erosion of the binary version of this image by the structuring element presented in Fig. 11, followed by an erosion of the complement of the binary image with the complement of the same ...
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... Fig. 10 an original image containing three objects of different shapes is presented. The goal in this case was to verify the presence of the middle object. An erosion of the binary version of this image by the structuring element presented in Fig. 11, followed by an erosion of the complement of the binary image with the complement of the same structuring element plus the intersection of these results can detect the required object as shown in Fig. ...
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... case was to verify the presence of the middle object. An erosion of the binary version of this image by the structuring element presented in Fig. 11, followed by an erosion of the complement of the binary image with the complement of the same structuring element plus the intersection of these results can detect the required object as shown in Fig. ...
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Citations
... Nowadays, computer vision has many applications like object recognition, movement tracking, face detection, stereopsis among others. However, it is extremely complicated to develop a robust algorithm that presents a minimum margin of error due the large number of variables and the large amount of information that must be processed [1][2][3][4][5]. Traditionally, object recognition is implemented by software, where elements, such as data handling, memory use or handling arithmetic operations, are not explicit considered. ...
... Traditionally, object recognition is implemented by software, where elements, such as data handling, memory use or handling arithmetic operations, are not explicit considered. Hardware implementation take into consideration all these elements with the aim of reducing mathematical complexity and optimizing the algorithm in order to use the least amount of resources possible [3][4][5]. ...
... For hardware implementation, it is necessary to reduce the algorithm complexity as we can find in [4][5], where generic algorithms of object detection were implemented in Field Programmable Gate Arrays (FPGA). Recently, a hardware implementation of the SURF extractor in combination with the Haar-like global feature was successfully implemented in a FPGA in [10]. ...
The present work shows the description of a simple fast shape detection algorithm and its implementation in hardware in a FPGA system. The detection algorithm is based on the concepts of Hu's moments which are invariant to similarity transformations. The recognition algorithm is implemented by using a non-local means filter. The algorithm is implemented on a FPGA system by using a hardware description language. We present the different design stages of the algorithm implementation which is based on the finite state machine technique. This algorithm is able to recognize a target shape over a test image. Furthermore, this work, describes the advantages of the implementation in hardware, such as speed and parallelism in signal processing. Finally, we show some results of the implementation of this algorithm.
... We usually use the method that combined the "host" with "FPGA" [22], and the host used in the control of training process of beginning and ending provides image data as input in the forward propagation. The application of FPGA based artificial neural network includes image segmentation [23], image and video processing [24], intelligent image analysis [25,26], autonomous robot technology [27], and sensorless control [28,29]. But because this kind of parallel method requires the programer to have the solid digital circuit knowledge and the programing complexity is high, it is barely used in practice. ...
With the development of the mobile systems, we gain a lot of benefits and convenience by leveraging mobile devices; at the same time, the information gathered by smartphones, such as location and environment, is also valuable for business to provide more intelligent services for customers. More and more machine learning methods have been used in the field of mobile information systems to study user behavior and classify usage patterns, especially convolutional neural network. With the increasing of model training parameters and data scale, the traditional single machine training method cannot meet the requirements of time complexity in practical application scenarios. The current training framework often uses simple data parallel or model parallel method to speed up the training process, which is why heterogeneous computing resources have not been fully utilized. To solve these problems, our paper proposes a delay synchronization convolutional neural network parallel strategy, which leverages the heterogeneous system. The strategy is based on both synchronous parallel and asynchronous parallel approaches; the model training process can reduce the dependence on the heterogeneous architecture in the premise of ensuring the model convergence, so the convolution neural network framework is more adaptive to different heterogeneous system environments. The experimental results show that the proposed delay synchronization strategy can achieve at least three times the speedup compared to the traditional data parallelism.
... Implementation of image processing algorithms on reprogrammable hardware devices with an ability of parallel processing became a 'hot' research topic, and plenty of work has been reported in the literature [1][2][3][4][5]. As the requirement of computationally intensive image-processing algorithms for real-time industrial applications, such as robotic vision, imposes high-speed and highly parallel implementations, in recent years a trend has been witnessed towards utilizing field programmable gate arrays (FPGAs) or graphics processing units (GPUs) instead of using CPUs, which are inherently sequential processing devices. ...
... As the requirement of computationally intensive image-processing algorithms for real-time industrial applications, such as robotic vision, imposes high-speed and highly parallel implementations, in recent years a trend has been witnessed towards utilizing field programmable gate arrays (FPGAs) or graphics processing units (GPUs) instead of using CPUs, which are inherently sequential processing devices. As an indication of this shift, one can encounter various image-processing applications implemented on hardware for real-time applications, such as shape recognition [1,4], medical image-processing [6], object detection [7][8][9][10], image retrieval application [11], and image encryption [12]. Parallel computation and reprogrammability are expected to offer a new path to the industrial application of computationally complex applications where shape detection plays a crucial role. ...
... i) First of all, edges G x and G y are obtained by applying horizontal and vertical Sobel filters, S h and S v , as given in Eqs. (1) and (2) on the input image I . ...
A hardware implementation of a computationally light, scale, and rotation invariant method for shape detection on FPGA is devised. The method is based on histogram of oriented gradients (HOG) and average magnitude difference function (AMDF). AMDF is used as a decision module that measures the similarity/dissimilarity between HOG vectors of an image in order to classify the object. In addition, a simulation environment implemented on MATLAB is developed in order to overcome the time-consuming and tedious process of hardware verification on the FPGA platform. The simulation environment provides specific tools to quickly implement the proposed methods. It is shown that the simulator is able to produce exactly the same results as those obtained from FPGA implementation. The results indicate that the proposed approach leads to a shape detection method that is computationally light, scale, and rotation invariant, and, therefore, suitable for real-time industrial and robotic vision applications.
... MM can be used for tasks such as noise removal, recognition of shapes and object center detection. An important feature of MM is the possibility of implementation on specialized hardware or FPGAs (Field Programmable Gate Array), where executions of morphological operations may be processed in parallel and thus, the processing can be improved as demonstrated by [14]. ...
... In some works it is possible to find applications of MM, as in [13], [14], [15] and [16], where this technique has shown significant results in relation to accuracy and image processing time. In [13] and [16] this technique uses binary images. ...
... As described in [21] 10 fps is a rate acceptable for visual servoing, though there are methods which are developed in specialized devices that can achieve higher rates. An important feature is that MM-based methods can be easily implemented on FPGAs, as in [14] where FPGAs are used for the processing of morphological operations, reaching rates of 60 fps on images of size 640 x 480 pixels. ...
Position-based visual servoing is a technique for vision-based robot control, which operates in the 3D workspace and uses a known model of the object to perform tasks of feature extraction and positioning. Among the many applications, position-based visual servoing is used in industrial environments, for object manipulation operations on conveyor belts. Mathematical morphology, a well-known computer vision technique, can be used for features extraction, representation of objects and to perform actions such as recognition by images. The representation of the object occurs with the assistance of a structuring element and the morphological operations are used to locate the object center. This work explores the binary mathematical morphology whose operators are trained by a reconfigurable system developed in a FPGA with the representation of the 3D model of the object to be applied in visual servoing in controlled applications such as tasks in industrial environments.
... Mathematical morphology is a powerful tool for image processing and analysis in a wide range of applications, including shape recognition [2], image processing [7], [8], video processing [9], [25], document authentication [14], [15], and computer vision [10], [11]. ...
Binary image processing is a powerful tool in many image and video applications. A reconfigurable processor is presented for binary image processing in this paper. The processor's architecture is a combination of a reconfigurable binary processing module, input and output image control units, and peripheral circuits. The reconfigurable binary processing module, which consists of mixed-grained reconfigurable binary compute units and output control logic, performs binary image processing operations, especially mathematical morphology operations, and implements related algorithms more than 200 f/s for a 1024 × 1024 image. The periphery circuits control the whole image processing and dynamic reconfiguration process. The processor is implemented on an EP2S180 field-programmable gate array. Synthesis results show that the presented processor can deliver 60.72 GOPS and 23.72 GOPS/mm2 at a 220-MHz system clock in the SMIC 0.18-μm CMOS process. The simulation and experimental results demonstrate that the processor is suitable for real-time binary image processing applications.
... Comparing the results with those obtained in the literature [30][15] [21] our implementation presented improvements in fitness, processing time and programming flexibility. Besides, the main idea of this implementation was to create a flexible linear procedure (opcode) that could be implemented by a reconfigurable processor, to achieve high performance processing [31] [32], this is the main difference in relation to other works found in the literature. In addition, the other systems that have been compared are able to process only binary images and the convolution instructions were not implemented by these works. ...
This paper presents a methodology for automatic construction of image operators using a linear genetic programming approach, for binary, gray level and color image processing, where the processing solution for a particular application is expressed in terms of the basic morphological operators, dilation and erosion, in conjunction with convolution and logical operators. Genetic Programming (GP), based on concepts of genetics and Darwin's principle of natural selection, to genetically breed and evolve computer programs to solve a wide variety of problems, is a branch of evolutionary computation, and it is consolidating as a promising methodology to be used in applications involving pattern recognition, classification problems and modeling of complex systems. Mathematical morphology is based on the set theory (complete lattice), where the notion of order is very important. This processing technique has proved to be a powerful tool for many computer vision tasks. However, the manual design of complex operations involving image operators is not trivial in practice. Thus, the proposed methodology tries to solve these drawbacks. Some examples of applications are presented and the results are discussed and compared with other methods found in the literature.
Digital image processing is mainly focused on ever expanding and dynamic area with applications reaching out into our day today life such as medicine, security purpose, space exploration, surveillance, identification & authentication, automatic industry inspection etc. Applications such as these involve different operations like image enhancement, object detection and Noise removing. Implementing the image processing applications on a computer can be easier one, but not efficient due to additional constraints on memory and other peripheral devices. However, most general purpose hardware is not suited for strong real-time constraints. This paper gives the implementation of median filter image processing on FPGA. The processor's architecture is combining with a reconfigurable binary processing module, input and output image controller units, and peripheral circuits. Reconfigurable binary processing module will perform median filter operations, for a 180×180 image. The periphery circuits control the whole image processing and dynamic reconfiguration process. The processor is implemented on an EP2C35 field-programmable gate array. The simulation and experimental results demonstrate that the processor is suitable for real-time binary image processing applications.
In the comparative analysis of image characteristics of shadow-free and shaded area, an algorithm for shaded area, avoiding the area whose illumination is weak and tending to the area with strong light via looking for the strongest and weakest light area, is established, which can thereby improve the efficiency of power generation. The result demonstrates that the method can find the region with the strongest sunlight fast and accurately.
