Figure 9 - available via license: Creative Commons Attribution 4.0 International
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Block diagram of the arithmetic unit (a) and grouping of M arithmetic units to calculate M terms of the multiplier operation in parallel (b).
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Concern for the security of embedded systems that implement IoT devices has become a crucial issue, as these devices today support an increasing number of applications and services that store and exchange information whose integrity, privacy, and authenticity must be adequately guaranteed. Modern lattice-based cryptographic schemes have proven to b...
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Context 1
... third block of Figure 5 contains the arithmetic units in charge of evaluating the terms that appear in the summation of Equation (3). As shown in Figure 9a, the fact that one of the polynomials involved in the operation is ternary allows simplifying the implementation of this element by reducing its functionality to add or subtract from the previously accumulated value of e(k) the value of the coefficient h(j) if the value of r(i) is 1 or −1, respectively. For a polynomial multiplier of degree of multiplicity M, M of these elementary blocks must be combined according to the scheme illustrated in Figure 9b, where the input and output buses are composed by concatenating the corresponding buses of each of the arithmetic units. ...
Context 2
... shown in Figure 9a, the fact that one of the polynomials involved in the operation is ternary allows simplifying the implementation of this element by reducing its functionality to add or subtract from the previously accumulated value of e(k) the value of the coefficient h(j) if the value of r(i) is 1 or −1, respectively. For a polynomial multiplier of degree of multiplicity M, M of these elementary blocks must be combined according to the scheme illustrated in Figure 9b, where the input and output buses are composed by concatenating the corresponding buses of each of the arithmetic units. ...
Citations
... On one hand, some studies are based on a high-level synthesis (HLS) methodology, starting from a high-level description of the NTRU algorithm [15]. On the other hand, some employ a methodology based on a register-transfer level (RTL) description for critical operations [16][17][18]. The main advantage of the first strategy is the reduction in development time due to the use of automatic synthesis tools that do not require a solid background of designers in hardware description languages. ...
... On the other hand, the use of fully parallel structures to reduce the number of cycles implies a high cost in terms of resources, which constrained implementations cannot afford. To solve these drawbacks, a low-resource architecture for NTRUEncrypt based on a partial parallelization of the scalar multiplications that does not present any security breach against timing attacks is proposed in [18]. In this case, the operation could be accelerated using only the 2 · dr nonzero coefficients of the polynomial r(x) (dr is the number of coefficients that are 1 and −1), i.e., r(x) ∈ T (dr), resulting in a number of operations equal to (N · 2dr) + (N − 2dr). ...
... In the NTRU Round 3 scheme [11], the coefficients of the polynomials r(x) and h(x) are computed as modulus 2 and modulus 2048, respectively. The efficient arithmetic unit (AU) presented in [16][17][18] has been slightly modified. The new architecture uses a logic gate AND instead of a multiplexer. ...
The advent of quantum computing with high processing capabilities will enable brute force attacks in short periods of time, threatening current secure communication channels. To mitigate this situation, post-quantum cryptography (PQC) algorithms have emerged. Among the algorithms evaluated by NIST in the third round of its PQC contest was the NTRU cryptosystem. The main drawback of this algorithm is the enormous amount of time required for the multiplication of polynomials in both the encryption and decryption processes. Therefore, the strategy of speeding up this algorithm using hardware/software co-design techniques where this operation is executed on specific hardware arises. Using these techniques, this work focuses on the acceleration of polynomial multiplication in the encryption process for resource-constrained devices. For this purpose, several hardware multiplications are analyzed following different strategies, taking into account the fact that there are no possible timing information leaks and that the available resources are optimized as much as possible. The designed multiplier is encapsulated as a fully reusable and parametrizable IP module with standard AXI4-Stream interconnection buses, which makes it easy to integrate into embedded systems implemented on programmable devices from different manufacturers. Depending on the resource constraints imposed, accelerations of up to 30–45 times with respect to the software-level multiplication runtime can be achieved using dedicated hardware, with a device occupancy of around 5%.
... The disadvantage of Karatsuba's algorithm is that for polynomials with degree n < 32, this algorithm is slower than unoptimized polynomial multiplication. To overcome this shortcoming, Karatsuba's algorithm is used only for those polynomials whose degree is greater than 32. 1 ees401ep1 112 401 3 2048 133 113 113 2 ees449ep1 128 449 3 2048 149 134 134 3 ees677ep1 192 677 3 2048 225 157 157 4 ees1087ep2 256 1087 3 2048 362 120 120 5 ees659ep1 112 659 3 2048 219 38 38 6 ees761ep1 128 761 3 2048 253 42 42 7 ees1087ep1 192 1087 3 2048 362 63 63 8 ees1499ep1 256 1499 3 2048 499 79 79 9 ees541ep1 112 541 3 2048 180 49 49 10 ees613ep1 128 613 3 2048 204 55 55 11 ees887ep1 192 887 3 2048 295 81 81 12 ees1171ep1 256 1171 3 2048 390 106 106 To ensure sufficient cryptographic strength of the algorithm, it is necessary to correctly choose the parameters N, q, and p. Table 1 presents parameters that are safe according to [24]. At the same time, parameter sets 1-4 provide the smallest key size for the required cryptographic strength, parameters 5-8 provide the best performance with a larger key size, and parameter sets 9-12 are selected so as to minimize the value of C for the required cryptographic strength level, which is calculated by the formula: C = S * t 2 (13) where t is the execution time of the algorithm and S is the total length of the public and private keys [25]. ...
This work is devoted to the development of a modification of the post-quantum public-key cryptosystem NTRUEncrypt. Given that two main requirements for modern cryptographic algorithms are resistance to attacks (including quantum attacks) and performance, the developed modification offers an improvement in both aspects. Karatsuba algorithm for fast polynomial multiplication is employed to achieve better performance. The modification also includes additional protection against a chosen ciphertext attack that can be effectively against standard NTRUEncrypt. Performance test of the developed modification confirmed that less time is required for key generation, encryption and decryption in comparison with the classical algorithm. The modified algorithm is then applied to implement an asymmetric encryption system with a graphical user interface that allows establishing communication between two users with resistance to both classical and quantum attacks.
... Internet of Things (IoT) solutions are provided in WSNs [7,8]. CPS is focused on serving a variety of applications, and is not restricted to specific nodes. ...
In the modern era of societal advancement, there is a notable reliance on information and communication technologies within engineering centers. This reliance underscores the importance of implementing effective organizational and technical measures to safeguard information resources. Ensuring compliance with necessary security standards and employing certified protective measures is imperative. Protecting the Engineering Center's information involves continuous monitoring and prompt response to any breaches compromising integrity, confidentiality, and availability. Identifying specific vulnerabilities that directly jeopardize these resources is essential. Moreover, safeguarding resources necessitates a comprehensive protection strategy encompassing software, technical, cryptographic, and organizational measures to uphold information security consistently.
The growing cognizance of spectrum scarcity has become a more significant concern in wireless radio communications. Due to the exponential growth of data transmission in intelligent wireless sensor networks, energy spectrum detection has become a promising solution for resolving spectrum shortages. Primary user emulation attack (PUEA) has been identified as a significant attack vector in the cognitive radio (CR) domain's physical layer. In comparison, the CR is a promising method to increase spectrum efficiency by allowing unlicensed secondary users (SUs) to access licensed frequency bands without interfering with approved primary users (PUs). The study's primary findings are the methodology for preventing PUEA using authentication tags, which are unique sequences. This research blends SC‐FDMA with CR to protect CR networks from PUEA attacks, a Latin square (LS) matrix tag generation system is proposed to mitigate the PUEA effect. The technology is meant to provide effective authentication and protection against malicious users. In a secured environment, the LS tag technique is utilized to track and estimate the PU. For example, the BER of both techniques is virtually identical between 0 and 4 dB, while the BER performance of the suggested LS tag generation improves with increasing signal‐to‐noise ratio (SNR). As a result, the suggested LS tag generation is less susceptible to PUEA. To diminish the influence of PUEA in CR networks, an efficient enlightening approach for making the future Green Cognitive Radio Wireless networks structure is proposed. The simulation results also demonstrate the resilience of the proposed CR spectrum sensing techniques for energy‐efficient knowledge at varying degrees to reduce the adverse effects of environmental technologies.
