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This paper presents a CMOS chip for the parallel acquisition and
concurrent analog processing of two-dimensional (2-D) binary images. Its
processing function is determined by a reduced set of 19 analog
coefficients whose values are programmable with 7-b accuracy. The
internal programming signals are analog, but the external control
interface is ful...
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... Boolean operator. Besides the parallel optical loading, images can also be loaded or downloaded, on a row by row basis, through an external I/O bidirectional bus. Finally, because the spatial boundary conditions also play an important role for processing, the cell array is surrounded by a ring of border cells with programmable output variable. Fig. 2 shows a block diagram of the cell analog processing circuitry, including different functional blocks: integrator, non- linearity, memory, and programmable interconnection synapse. These latter are time-multiplexed, meaning that the 18 param- eters associated to the feedback and the control templates are implemented using only nine ...
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Citations
... Focalplane sensor-processor Arrays (FPSPs) add a processor per pixel, where it is possible to do some level of processing before going through the ADC. Example FPSPs include ACE400 (Dominguez-Castro et al., 1997), ACE16k (Linan et al., 2002), MIPA4K (Poikonen et al., 2009), and SCAMP (SIMD current-mode analog matrix processor) chips (Dudek and Hicks, 2005) , (Carey et al., 2013b). More details about SCAMP-5 FPSP is presented in the next section. ...
Robotics faces a long-standing obstacle in which the speed of the vision system’s scene understanding is insufficient, impeding the robot’s ability to perform agile tasks. Consequently, robots must often rely on interpolation and extrapolation of the vision data to accomplish tasks in a timely and effective manner. One of the primary reasons for these delays is the analog-to-digital conversion that occurs on a per-pixel basis across the image sensor, along with the transfer of pixel-intensity information to the host device. This results in significant delays and power consumption in modern visual processing pipelines. The SCAMP-5—a general-purpose Focal-plane Sensor-processor array (FPSP)—used in this research performs computations in the analog domain prior to analog-to-digital conversion. By extracting features from the image on the focal plane, the amount of data that needs to be digitised and transferred is reduced. This allows for a high frame rate and low energy consumption for the SCAMP-5. The focus of our work is on localising the camera within the scene, which is crucial for scene understanding and for any downstream robotics tasks. We present a localisation system that utilise the FPSP in two parts. First, a 6-DoF odometry system is introduced, which efficiently estimates its position against a known marker at over 400 FPS. Second, our work is extended to implement BIT-VO—6-DoF visual odometry system which operates under an unknown natural environment at 300 FPS.
... Considering only the first denominator term of this approximation and approximating the terms below, we have the following approximation given in Eq. (22). →0 ...
The memristance of a memristor depends on the amount of charge flowing through it and when current stops flowing through it, it remembers the state. Thus, memristors are extremely suited for implementation of memory units. Memristors find great application in neuromorphic circuits as it is possible to couple memory and processing, compared to traditional Von-Neumann digital architectures where memory and processing are separate. Neural networks have a layered structure where information passes from one layer to another and each of these layers have the possibility of a high degree of parallelism. CMOS-Memristor based neural network accelerators provide a method of speeding up neural networks by making use of this parallelism and analog computation. In this project we have conducted an initial investigation into the current state of the art implementation of memristor based programming circuits. Various memristor programming circuits and basic neuromorphic circuits have been simulated. The next phase of our project revolved around designing basic building blocks which can be used to design neural networks. A memristor bridge based synaptic weighting block, a operational transconductor based summing block were initially designed. We then designed activation function blocks which are used to introduce controlled non-linearity. Blocks for a basic rectified linear unit and a novel implementation for tan-hyperbolic function have been proposed. An artificial neural network has been designed using these blocks to validate and test their performance. We have also used these fundamental blocks to design basic layers of Convolutional Neural Networks. Convolutional Neural Networks are heavily used in image processing applications. The core convolutional block has been designed and it has been used as an image processing kernel to test its performance.
... The memristor representing a synapse weight is implemented in cross point of every two wires. It can perform many parallel analog dot product calculations as (10) where V in , V out , and I c are the input signal, the output signal, and the current, respectively. G denotes the memristor conductance value, R m is the sensitive resistance value of the operational amplifier. ...
Memristor with memory properties can be applied to connection points (synapses) between cells in a cellular neural network (CNN). This paper highlights memristor crossbar-based multilayer CNN (MCM-CNN) and its application to edge detection. An MCM-CNN is designed by adopting a memristor crossbar composed of a pair of memristors. MCM-CNN based on the memristor crossbar with changeable weight is suitable for edge detection of a binary image and a color image considering its characteristics of programmablization and compactation. Figure of merit (FOM) is introduced to evaluate the proposed structure and several traditional edge detection operators for edge detection results. Experiment results show that the FOM of MCM-CNN is three times more than that of the traditional edge detection operators.
... Owing to the localized synaptic connections or communication between cells and the fully parallel operations of each cell, it is more suitable to be implemented with the hardware within the neuromorphic regime. Memristive synapses can further reduce the area cost compared with a CMOS only solution (Dominguez-Castro et al., 1997). Simulation results have shown that memristive cellular neural networks execute functions of image processing such as horizontal line detection, edge extraction, and noise removal (Duan et al., 2015). ...
Memristive devices share remarkable similarities to biological synapses, dendrites, and neurons at both the physical mechanism level and unit functionality level, making the memristive approach to neuromorphic computing a promising technology for future artificial intelligence. However, these similarities do not directly transfer to the success of efficient computation without device and algorithm co-designs and optimizations. Contemporary deep learning algorithms demand the memristive artificial synapses to ideally possess analog weighting and linear weight-update behavior, requiring substantial device-level and circuit-level optimization. Such co-design and optimization have been the main focus of memristive neuromorphic engineering, which often abandons the “non-ideal” behaviors of memristive devices, although many of them resemble what have been observed in biological components. Novel brain-inspired algorithms are being proposed to utilize such behaviors as unique features to further enhance the efficiency and intelligence of neuromorphic computing, which calls for collaborations among electrical engineers, computing scientists, and neuroscientists.
... This advancement of CMOS technology means that massively parallel processing or pixel-parallel processing is becoming more feasible. Considerable research has been published, for example, on vision chips based on cellular neural networks (CNN) [51][52][53][54], programmable multiple instruction and multiple data (MIMD) vision chips [55], biomorphic digital vision chips [56], and analog vision chips [57,58]. Other pioneering works include digital vision chips using pixel-level processing based on single instruction and multiple data (SIMD) processor by M. Ishikawa et al. at the University of Tokyo and Hamamatsu Photonics [59][60][61][62][63][64][65]. ...
... The two main arithmetic operations required for hardware implementation of neural networks are 1) multiplication and 2) summation performed in synapses and neuron body (soma), respectively. One of the leading studies in the hardware realization of neural networks is Cellular Neural Network where a simplified Gilbert multiplier with eight transistors is used for analog multiplication and summation is performed via simple wired connection after converting the signals to current mode [5]. However, the large number of transistors required to implement the neuron is a serious bottleneck for the development of a circuit-based neural network. ...
Nonlinear memristor-based neural network and a circuit-based learning system is addressed in this work. The weights of the neural network are based on the memristor bridge synapse and the learning architecture is designed in analog-digital mixed circuits by adopting a simple learning algorithm called random weight change algorithm. Though the memristor bridge can be efficiently used as a synapse, it still suffers from nonlinearity in weight programming at its extremes due to the boundary effect of memristors, which is a common phenomenon in most of the nano-devices. In this study, a novel architecture of a modified memristor bridge synapse is proposed that avoids the boundary effect issue by shifting the programming origin to the middle of the linear region. To demonstrate the effectiveness of the proposed method, multilayer neural network along with the end-to-end learning architecture is designed in circuit with nonlinear memristors and tested for several classical learning problems. Simulation results showing successful learning and correct behavior of replicated neural network are presented.
... These energy overheads pose difficulties to implement such systems in embedded, energy-constraint environments. Focal-plane processor devices [50], such as ACE400 [14], ACE16K [30], MIPA4K, [37], and the various iterations of the SCAMP (SIMD current-mode analog matrix processor) chip [8,15,16,18] try to address this problem by shifting image processing from a dedicated processing unit onto the image sensor's focal plane, by adding processing elements to each pixel. Unlike traditional computers, most of the chips mentioned above, including the SCAMP-5 [8], which is the focus of the article, store the captured and intermediate images as analogue instead of digital values. ...
Focal-plane Sensor-Processor Arrays (FPSPs) are new imaging devices with parallel Single Instruction Multiple Data (SIMD) computational capabilities built into every pixel. Compared to traditional imaging devices, FPSPs allow for massive pixel-parallel execution of image processing algorithms. This enables the application of certain algorithms at extreme frame rates (>10,000 frames per second). By performing some early-stage processing in-situ, systems incorporating FPSPs can consume less power compared to conventional approaches using standard digital cameras. In this article, we explore code generation for an FPSP whose 256 × 256 processors operate on analogue signal data, leading to further opportunities for power reduction—and additional code synthesis challenges.
While rudimentary image processing algorithms have been demonstrated on FPSPs before, progress with higher-level computer vision algorithms has been sparse due to the unique architecture and limits of the devices. This article presents a code generator for convolution filters for the SCAMP-5 FPSP, with applications in many high-level tasks such as convolutional neural networks, pose estimation, and so on. The SCAMP-5 FPSP has no effective multiply operator. Convolutions have to be implemented through sequences of more primitive operations such as additions, subtractions, and multiplications/divisions by two. We present a code generation algorithm to optimise convolutions by identifying common factors in the different weights and by determining an optimised pattern of pixel-to-pixel data movements to exploit them. We present evaluation in terms of both speed and energy consumption for a suite of well-known convolution filters. Furthermore, an application of the method is shown by the implementation of a Viola-Jones face detection algorithm.
... Cellular vision chips, such as the ACE400 [55], ACE16K [56], MIPA4K [57], and Focal-plane Sensor-Processor Arrays (FPSPs) [58], [59], [60], integrate sensing and processing in the focal plane. FPSPs are massively parallel processing systems on a single chip. ...
Visual understanding of 3D environments in real-time, at low power, is a huge computational challenge. Often referred to as SLAM (Simultaneous Localisation and Mapping), it is central to applications spanning domestic and industrial robotics, autonomous vehicles, virtual and augmented reality. This paper describes the results of a major research effort to assemble the algorithms, architectures, tools, and systems software needed to enable delivery of SLAM, by supporting applications specialists in selecting and configuring the appropriate algorithm and the appropriate hardware, and compilation pathway, to meet their performance, accuracy, and energy consumption goals. The major contributions we present are (1) tools and methodology for systematic quantitative evaluation of SLAM algorithms, (2) automated, machine-learning-guided exploration of the algorithmic and implementation design space with respect to multiple objectives, (3) end-to-end simulation tools to enable optimisation of heterogeneous, accelerated architectures for the specific algorithmic requirements of the various SLAM algorithmic approaches, and (4) tools for delivering, where appropriate, accelerated, adaptive SLAM solutions in a managed, JIT-compiled, adaptive runtime context.
... Furthermore, although additional circuits must be designed for computing the synaptic weighting, they are limiting the operation of the synapse to a certain range of voltages [3]. Some successful implementations of cellular networks have already been reported [7]- [9], however its hardware implementation is still a challenging task, in order to achieve all the requirements described above. ...
... )dτ is the magnetic flux of each memristor. Hence, v AB (t) and the ξ weight are obtained as vAB(t) = αvm(t)(ϕM 1 (t) + ϕM 2 (t)), ξ = vAB(t)/vm(t) (7) From (2), the memristance variation for M 2 (ϕ M2 (t)) is Similarly, M 1 (ϕ M1 (t) can be expressed as ...
... where γ 2 and β 2 is the slope and intercept of triangular wave respectively. It is worth to stress that the v AB (t) voltage given by (7) has been computed in terms of the magnetic flux. According to Fig. 2, v AB (t) can also be computed in terms of memristances as ...
... Figure 3b,c are equivalent circuits. [17,18]. Figure 3 shows a structure of a memristor fabricated successfully by HP [2]. ...
... An analog multiplier employed to implement Cellular Neural Networks [17,18]. Figure 3 shows a structure of a memristor fabricated successfully by HP [2]. ...
