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Block diagram of the TMC-PHX1 chip.
Source publication
A high-precision time-to-digital-converter VLSI, TMC-PHX1, was
developed for the PHENIX drift chamber. The chip contains 4 channels of
TDC with two stages of data buffering and one level of trigger buffering
required in very high rate experiments. In addition to a fixed data size
readout, the chip also supports a zero-suppression mode readout. The...
Context in source publication
Citations
... A time memory cell (TMC) was proposed by Y. Arai et al. and applied to measure the drift times of electrons [3]. This cell harnesses the low-power and high-density characteristics of a CMOS memory cell and the short delay time of a gate. ...
We propose SOI pixel circuits with a synchronized time memory cell (TMC) for
time-of-flight stigmatic imaging mass spectrometry. The circuits simultaneously
detect the position and the fine/coarse flight time of an ion for the MALDI-ToF
mass spectrometer. We discuss the circuit design and present the simulation
results of a prototype detector comprised of a 32 x 32 pixel array in which
each pixel pitch is 40 um and the time resolution is a minimum of 1 ns. The
results of transient analysis demonstrate the fully correct synchronous
operation at a 100-MHz clock frequency and simultaneous 32-word SRAM writing.
... B Over the past decades, jitter related issues are studied in the several research areas, which include data communications [6, 7, 8], testing instruments for device physics [9, 10, 11], and clock generation circuits for high-performance systems [12, 13, 14, 15, 6, 16]. In contrast, researchers have given little attention to the jitter issues in the context of signal distribution methodology in high-performance systems. ...
Timing jitter in long on-chip interconnects has become an increasingly important issue in signal integrity and timing violations. In this paper, we focus on cycle-to-cycle jitter induced by repeater power supply noise in both point-to-point and branched RC and RLC interconnects in 70nm CMOS. We develop an analytical expression for jitter based on propagation delay variation that accurately predicts HSPICE simulation results. We show the difference in impact between RC and RLC wire models on jitter (up to 64%). We also show a method for jitter-optimal repeater insertion which differs from conventional delay optimal insertion methods, resulting in larger repeaters. Finally, we introduce methods which can decrease timing violations in branched global interconnects by adjusting repeater size and tuning the phase of the power supply noise.
... We have been developing several kinds of VME TDC modules [1, 2] which use our custom-developed Time Memory Cell (TMC) chips [3]. A new TMC chip, TMC-PHX1 [4], was recently developed for the drift chamber readout of the PHENIX experiment at the RHIC accelerator. To utilize the advanced performance of the chip in a small test experiments, we have developed a new VME TDC module by using the TMC-PHX1 chip. ...
... Specification of the TMC-PHX1 chip [4] is summarized inTable 1. There are 4 input channels in the chip. ...
A new 32-channel pipeline TDC module, which implements
custom-developed Time Memory Cell LSIs, has been developed for high-rate
wire-chamber applications. Time resolution of the module is 300 ps
r.m.s., and the time range is 6.4 μsec. For handling data transfer
and controlling the module, a 40 MHz digital signal processor is
implemented in the module. Most of the control logic is implemented in
two complex PLDs to achieve a density of 32 channels in a single-width,
double height VME module
Semiconductor sensors patterned at the micron scale combined with custom-designed integrated circuits have revolutionized semiconductor radiation detector systems. Designs covering many square meters with millions of signal channels are now commonplace in high-energy physics and the technology is finding its way into many other fields, ranging from astrophysics to experiments at synchrotron light sources and medical imaging. This book presents a discussion of the many facets of highly integrated semiconductor detector systems, covering sensors, signal processing, transistors, circuits, low-noise electronics, and radiation effects. To lay a basis for the more detailed discussions in the book and aid in understanding how these different elements combine to form functional detector systems, the text includes introductions to semiconductor physics, diodes, detectors, signal formation, transistors, amplifier circuits, electronic noise mechanisms, and signal processing. A chapter on digital electronics includes key elements of analog-to-digital converters and an introduction to digital signal processing. The physics of radiation damage in semiconductor devices is discussed and applied to detectors and electronics. The diversity of design approaches is illustrated in a chapter describing systems in high-energy physics, astronomy, and astrophysics. Finally, a chapter 'Why things don't work', discusses common pitfalls, covering interference mechanisms such as power supply noise, microphonics, and shared current paths ('ground loops'), together with mitigation techniques for pickup noise reduction, both at the circuit and system level. Beginning at a basic level, the book provides a unique introduction to a key area of modern science.
The PHENIX On-Line system takes signals from the Front End Modules (FEM) on each detector subsystem for the purpose of generating events for physics analysis. Processing of event data begins when the Data Collection Modules (DCM) receive data via fiber-optic links from the FEMs. The DCMs format and zero suppress the data and generate data packets. These packets go to the Event Builders (EvB) that assemble the events in final form. The Level-1 trigger (LVL1) generates a decision for each beam crossing and eliminates uninteresting events. The FEMs carry out all detector processing of the data so that it is delivered to the DCMs using a standard format. The FEMs also provide buffering for LVL1 trigger processing and DCM data collection. This is carried out using an architecture that is pipelined and deadtimeless. All of this is controlled by the Master Timing System (MTS) that distributes the RHIC clocks. A Level-2 trigger (LVL2) gives additional discrimination. A description of the components and operation of the PHENIX On-Line system is given and the solution to a number of electronic infrastructure problems are discussed.
The PHENIX tracking system consists of Drift Chambers (DC), Pad Chambers (PC) and the Time Expansion Chamber (TEC). PC1/DC and PC2/TEC/PC3 form the inner and outer tracking units, respectively. These units link the track segments that transverse the RICH and extend to the EMCal. The DC measures charged particle trajectories in the r–φ direction to determine pT of the particles and the invariant mass of particle pairs. The PCs perform 3D spatial point measurements for pattern recognition and longitudinal momentum reconstruction and provide spatial resolution of a few mm in both r–φ and z. The TEC tracks particles passing through the region between the RICH and the EMCal. The design and operational parameters of the detectors are presented and running experience during the first year of data taking with PHENIX is discussed. The observed spatial and momentum resolution is given which imposes a limitation on the identification and characterization of charged particles in various momentum ranges.
Typescript. Thesis (M.S.E.C.E.)--University of Massachusetts Amherst, 2006. Includes bibliographical references (leaves 99-101).
In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential nonlinearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is proposed that will enable the measurement device to be synthesized from a register transfer level (RTL) description. Furthermore, as test time is an important consideration during a production test, a method is provided that reduces test time at the expense of more hardware. Experimental results on an FPGA implementation are provided as proof of concept. An IC prototype has also been designed and submitted for fabrication. Implementation details are provided in this paper
Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay line (VDL). An important drawback to the VDL structure is that its measurement accuracy depends on the matching of the various delay elements. Although careful layout techniques can help to minimize these mismatches, it cannot eliminate them completely. As well, due to the nature of the design, a relatively large silicon area is required for silicon implementation. In this paper, a novel technique is developed which reduces the silicon area requirements by two orders of magnitude, as well enables the measurement device to be synthesized from a register transfer level (RTL) description. A custom IC was designed and fabricated in a 0.18-/spl mu/m CMOS process as a first proof of concept. The design requires a silicon area of 0.12 mm/sup 2/ and measured results indicate a timing resolution of 19 ps. The synthesizable nature of the design is demonstrated using an field-programmable gate-array implementation. As test time is an important consideration for a production test, an extension to the component-invariant VDL technique is provided that reduces test time at the expense of more hardware. Finally, a method for obtaining the frequency domain characteristics of the jitter using the VDL will also be given.
