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A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband block...
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... error performance is verified up front in the bit-accurate model phase and hence the Verilog HDL model is synthesized and optimized to meet the other requirements, namely, speed and area. A signal path of the DFE for LTE CA consists of FIR1 (CIC filter), FIR3 (Farrow interpolator) [16], digital mixer, FIR4 (carrier aggregation filter or CAF), and FIR5 (channel selection filter or CSF), as exhibited in Figure 3. In order to process both the in-phase and quadrature signals, a pair of CIC filters and Farrow interpolators are employed [17]. ...
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... quad of carrier aggregation filters and channel selection filters exist to accommodate in-phase and quadrature signals and two carriers (carrier1 and carrier 2) in CA. FIR2 shown as a shaded box in Figure 3 may serve as an antidrooping filter in an attempt to partly cancel the drooping in the CIC filter and Farrow interpolator, which is not necessary in the current version. ...
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... RF phase-locked loop (PLL) reference clock can be set to 26 MHz, 39 MHz, 45.5 MHz, and 52 MHz for the overall DFE in Figure 3 and an active-low synchronous reset was used to initialize the register values. The mode select signal, casenr, determines which frequency mode was adopted for the LTE DFE. ...
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... critical path in the ASIC (180 nm CMOS) is highlighted in red in Figure 30, which includes a (15-bit × 23-bit) signed multiplier and a 26-bit adder. In the case of FIR5-carrier 1, the critical path delay was the delay of (the first flip-flop + multiplier + adder) delay, which amounted to 17.11 ns while in case of FIR5-carrier 2, the critical path delay was 16.40 ns. ...
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... the case of FIR5-carrier 1, the critical path delay was the delay of (the first flip-flop + multiplier + adder) delay, which amounted to 17.11 ns while in case of FIR5-carrier 2, the critical path delay was 16.40 ns. The critical path in the XC6VLX550T FPGA after the P&R is highlighted in green in Figure 30. Identical with FIR4, FIR5 in the FPGA also had a multiplier and an adder in the critical path, as with FIR5 in the ASIC. ...
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... than the ASIC synthesis results, the FPGA (XC6VLX550T) P&R results show that FIR3 (Farrow interpolator), involving many multipliers, consumed resources most, which used the largest number of DSP slices. The resources used by the DFE building blocks are summarized in Figure 33. Since FIR1 (CIC filter) did not use any multiplier, it did not use any DSP slice. ...
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... 1% of the FPGA slice registers were used for all the building blocks in the DFE and only 2% of the LUTs were used while 24% of the DSP slices were used. Pie graphs for the use of slice registers, LUTs, and DSP slices are shown in Figures 34-36, respectively. After the FPGA implementation, speed performance was obtained, which reflects the routing effect as well. ...
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... P&R is carried out individually for each building block. An example (5 MHz + 5 MHz) CA case was tested and the P&R timing report is shown in Figure 37. ISE (integrated synthesis environment) delay is the delay obtained after the FPGA P&R. ...
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... overall design process of the proposed DFE is shown in Figure 38, composed of three stages, namely, calculation of the filter specification, calculation of the filter coefficients, and simulation of the DFE together with the OFDM receiver model. From the chosen decimation ratio of each filter, the filter specification was calculated, followed by the calculation of the FIR filter coefficients. ...
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... the SNR is not met or if more than enough margin is left for the filter specification, this process is repeated to explore the design space and to optimize the overall system through manual tweaking of the decimation ratio, the filter specification, and the bitwidths, in this order. This design process was more specified with a simple example for each stage of the design process in Figure 38. The first stage of the design process in Figure 38 was the calculation of the filter specification. ...
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... design process was more specified with a simple example for each stage of the design process in Figure 38. The first stage of the design process in Figure 38 was the calculation of the filter specification. To explain the first stage, three design options are illustrated in Figure 39, differing in the respective decimation ratios across the CIC filter, the FSRC filter, and the FIR4 filter. ...
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... first stage of the design process in Figure 38 was the calculation of the filter specification. To explain the first stage, three design options are illustrated in Figure 39, differing in the respective decimation ratios across the CIC filter, the FSRC filter, and the FIR4 filter. The decimation ratio of each filter determines the sampling rate or frequency fs of the filter. ...
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... filter coefficients themselves were obtained on the basis of Parks-McClellan optimal FIR filter algorithm [26]. Finally, corresponding to the third stage of the design process in Figure 38, the overall DFE with the OFDM receiver model was simulated after the filter coefficients of all the filters are obtained. , and (c), respectively. ...
Citations
... When a 10-MHz Long-Term Evolution (LTE) channelization standard was used, the spectrum shifting procedure needed a few memory units, one multiplier, and one adder. [14] provided a more detailed design that complied with the timing constraints of 10-MHz LTE channelization, provided a more complex technique that adhered to the timing constraints of 10-MHz LTE channelization, with an FPGA implementation of the UFMC transmitter. However, the design methodologies for changing the filter type and length in the UFMC transmitter remain unknown, as do the read-only memory (ROM)-based approaches for directly storing the sine/ cosine values for the IDFT/IFFT unit and pulse-shaping filter sample points [15,16]. ...
... where, i = 0, i = 1, and i = 2 and μ 0 , μ 1 and μ 2 . The first three condition matrices (14) make up the main state matrix (15), which includes components R11 and R21 in Eq. (16). ...
... To reduce computation and storage, it is more efficient to adjust the sample rate in a series of decimation or interpolation filter stages than in a single-stage filter with a huge No. of filter taps [1], [2]. Formerly, we designed and implemented a DFE Rx with a cascaded integrator comb filter and a fractional sample rate converter [3] whereas in this work the fractional sample rate converter [2], [4], [5] is avoided to lower the complexity of the overall DFE. ...
... A systematic top-down strategy is taken to design and implement the proposed DFE from the algorithm level to the ASIC hardware level, which is described in great detail in [3] that we formerly authored. The design methodology and principle used to implement the proposed DFE in this work is also described in [3]. ...
... A systematic top-down strategy is taken to design and implement the proposed DFE from the algorithm level to the ASIC hardware level, which is described in great detail in [3] that we formerly authored. The design methodology and principle used to implement the proposed DFE in this work is also described in [3]. We formerly modeled, designed, and implemented a DFE Rx with fractional sample rate conversion in an ASIC [3]. ...
A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.
Realising a low-complexity Farrow channelisation algorithm for multi-standard receivers in software-defined radio is a challenging task. A Farrow filter operates best at low frequencies while its performance degrades towards the Nyquist region. This makes wideband channelisation in software-defined radio a challenging task with high computational complexity. In this paper, a hybrid Farrow algorithm that combines a modulated Farrow filter with a frequency response interpolated coefficient decimated masking filter is proposed for the design of a novel filter with low computational complexity. A design example shows that the HFarrow filter bank achieved multiplier reduction of 50%, 70% and 64%, respectively, in comparison with non-uniform modulated discrete Fourier transform (NU MDFT FB), coefficient decimated filter bank (CD FB) and interpolated coefficient decimated (ICDM) filter algorithms. The HFarrow filter bank is able to provide the same number of sub-band channels as other algorithms such as non-uniform modulated discrete Fourier transform (NU MDFT FB), coefficient decimated filter bank (CD FB) and interpolated coefficient decimated (ICDM) filter algorithms, but with less computational complexity.
