Figure - available from: Analog Integrated Circuits and Signal Processing
This content is subject to copyright. Terms and conditions apply.
Block diagram of front end wireless receiver

Block diagram of front end wireless receiver

Source publication
Article
Full-text available
In this paper a complex filter is presented where the shift in the frequency is obtained using a linear frequency transformation. The linear frequency transformation in the proposed design is implemented using a complex impedance. A complex impedance is also proposed in this paper using a Fully Balanced Second Generation Current Conveyor (FBCCII)....

Similar publications

Article
Full-text available
This paper presents a low-voltage, low-power and fault-tolerant implementation of Double Sideband Suppressed Carrier (DSB-SC) amplitude modulator-demodulator circuit for portable communication systems. Through the approximation proposed in this work, a CMOS four quadrant multiplier is used as a (de)modulator circuit to generate DSB-SC (de)modulated...

Citations

Article
Full-text available
In this paper, a bulk driven quadrature filter is proposed for low power applications. A 3rd complex filter is designed by cascade connection of 2nd order right shifted Low Pass Filter with first order right shifted notch filter, which helps in improving the selectivity of the filter. The quadrature filter is implemented by employing Fully Differential Current Conveyor (FDCCII) as a basic building block. The proposed quadrature filter achieves a −3 dB bandwidth of 1.3 MHz with an Image Rejection Ratio (IRR) of 22.5 dB. The design consumes a total power of 10.94 μW with Total Harmonic Distortion (THD) of 0.121 %\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\%$$\end{document}. The Figure Of Merit (FOM) of the proposed filter is 0.002fJ with a SFDR of 61 dB. The output noise of the design at 2 MHz centre frequency is 89.12 nV/Hz\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\sqrt{Hz}$$\end{document} and integrated Input Referred noise is 36.89 μVrms\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu V_{rms}$$\end{document}. The design is simulated using a 180 nm CMOS technology with a supply voltage of 0.5 V. The proposed quadrature filter is used for low-Intermediate Frequency (IF) receiver for standard IEEE 802.15.1 (Bluetooth) applications.