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Block diagram of a typical optical transmitter.

Block diagram of a typical optical transmitter.

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This letter presents a linear wideband differential optical driver amplifier in a 90-nm silicon germanium (SiGe) bipolar-complementary-metal-oxide-semiconductor (BiCMOS) process. The amplifier utilizes a modified triple-stacked heterojunction bipolar transistor (HBT) topology with emitter degeneration to achieve high output voltage swing and high l...

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... HE demand for high-speed optical communication systems has been increasing significantly [1]. Fig. 1 shows a block diagram of an optical transmitter front-end with an external modulator. An optical transmitter configuration typically includes an external Mach-Zehnder modulator (MZM), which requires a large driving voltage of more than 3-V peakto-peak differential (V ppd ) with linearity less than 6% total harmonic distortion (THD) ...

Citations

... Various demonstrations have been introduced in III-V technologies, such as gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP) [5], [6], [7]. In addition, silicon-based processes, such as complementary metal-oxide-semiconductors (CMOS), silicon on insulator (SOI), and silicon germanium (SiGe), are also heavily investigated [8], [9], [10], [11], [12]. ...
... InP has been proven to be a good technology at frequencies beyond 100 GHz with typical process parameters reported in [3] and [6] that offers high cutoff frequency fT, high breakdown voltage, low loss substrate, and reasonable efficiency [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24]. A 175-GHz InP distributed amplifier (DA) is presented in [23] that achieves 10-dBm output power and 12 dB of gain. ...
... In [24], an 11.5-dBm output power with 13 dB of gain DA covering more than 110-GHz bandwidth is presented. Several design techniques have also been introduced to improve the output power, gain, and bandwidth of InP DAs [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20]. Specifically, stack configurations of up to three heterojunction bipolar transistor (HBT) devices have been deployed for InP amplifiers to increase the power up to 100 mW [12], [13], [14], [15], [16], [17], [18], [19]. ...
Article
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In this letter, we present the designs and development of a wideband, high output power quadruple-stacked heterojunction bipolar transistor (HBT) distributed amplifier (DA). In particular, the stacked HBT configuration can improve gain and output power while achieving a very wide bandwidth. To validate the proposed design concept, a quadruple-stacked HBT DA is designed in an indium phosphide (InP) process. The measurement results show an average gain of 16 dB from 7–115-GHz bandwidth with a maximum of 24-dBm saturated output power ( $P_{\mathrm{sat}})$ . To the best of the authors’ knowledge, this is the first time quadruple-stacked HBT is used in a DA to achieve the highest output power compared with other published work in the same frequency range.
... Future mobile networks supporting the sixth generation (6G) technology require high performance systems that can manage high amount of data. For this case, power amplifiers (PAs) play an important role in the wireless communication systems [1][2] and they must be of high performance in terms of output power (P out ), power gain (G p ), and power added efficiency (P AE) [3]. Concurrently achieving these three significant specifications is not straightforward and requires multiobjective optimization-based methods. ...
Chapter
This study presents an automated power amplifier (PA) design process by optimizing the topology and values of design parameters, sequentially. The automated optimization environment is created with the combination of an electronic design automation tool and a numerical analyzer. As a first step, the configuration of the PA is generated using the bottom-up optimization (BUO) method, then the values of the components are optimized using the particle swarm optimization (PSO) algorithm that is employed with a shallow neural network. The PSO method is applied for optimizing PA in terms of output power, power gain, and efficiency leading to obtain optimal design parameters. The proposed optimization process is automatic and compact leading to reduce interruptions of designers during the process. In order to verify the effectiveness of the presented method, one lumped element PA including GaN HEMT transistor is designed and optimized. The optimized PA reveals higher than 45% power added efficiency with the linear gain performance between 10÷14.6 dB in the frequency band of 1÷2.3 GHz.