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A time-domain analog spatial compressed sensing encoder for neural recording applications is proposed. Owing to the advantage of MEMS technologies, the number of channels on a silicon neural probe array has doubled in 7.4 years, and therefore, a greater number of recording channels and higher density of front-end circuitry is required. Since neural...
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... can convert the time difference between two input clock edges into a digital code with high time resolution by using a delay time of logic elements. Figure 8 shows the block diagram of a delay-line-based and a ring-oscillator-based TDC. The delay-line-based TDC, which is shown in Figure 8a, is composed of a delay line, a D-FF array, and a decoder. ...
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... 8 shows the block diagram of a delay-line-based and a ring-oscillator-based TDC. The delay-line-based TDC, which is shown in Figure 8a, is composed of a delay line, a D-FF array, and a decoder. The TDC converts the time difference between the rising edges of the START and STOP signals. ...
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... the desired resolution is 10 bit, a 1024-stage delay line is required. On the other hand, a ring-oscillator-based TDC, which is shown in Figure 8b, is composed of a ring oscillator, a binary counter, a D-FF array, and a decoder. In the ring-oscillator type TDC, the D-FF array captures the phase of the ring oscillator for fine conversion, and the counter measures the ring oscillator output for coarse conversion. ...
Citations
... At the same time, the engineering community has focused on designing more efficient neural interfaces. Recent designs, aimed at reducing the quantity of raw data generated by conventional neural interfaces, Articles NaTUre BIoMeDICal eNgINeerINg use a wide range of techniques, such as on-chip thresholding [30][31][32] , on-chip spike sorting 33 , on-chip compression [34][35][36][37] and compressive sensing 38,39 . Despite these efforts, there is not yet a consensus on the required specifications for iBCI-oriented neural interfaces. ...
The efficacy of wireless intracortical brain–computer interfaces (iBCIs) is limited in part by the number of recording channels, which is constrained by the power budget of the implantable system. Designing wireless iBCIs that provide the high-quality recordings of today’s wired neural interfaces may lead to inadvertent over-design at the expense of power consumption and scalability. Here, we report analyses of neural signals collected from experimental iBCI measurements in rhesus macaques and from a clinical-trial participant with implanted 96-channel Utah multielectrode arrays to understand the trade-offs between signal quality and decoder performance. Moreover, we propose an efficient hardware design for clinically viable iBCIs, and suggest that the circuit design parameters of current recording iBCIs can be relaxed considerably without loss of performance. The proposed design may allow for an order-of-magnitude power savings and lead to clinically viable iBCIs with a higher channel count.
... These techniques are known as temporal compression techniques as they reduce the data recorded on individual channels in the time domain. Categorized under spatial compression techniques, there are ideas for spatial redundancy reduction, which are based on a modified whitening transform [11] and compressed sensing [12], respectively. This paper proposes a lossless data reduction approach, which is based on the elimination of spatial redundancy of multiple channels of neural signals, concurrently recorded using multi-electrode arrays. ...
This paper introduces a lossless approach for data reduction in multi-channel neural recording microsystems. The proposed approach benefits from eliminating the redundancy that exists in the signals recorded from the same space in the brain, e.g., local field potentials in intra-cortical recording from neighboring recording sites. In this approach, a single baseline component is extracted from the original neural signals, which is treated as the component all the channels share in common. What remains is a set of channel-specific difference components, which are much smaller in word length compared to the sample size of the original neural signals. To make the proposed approach more efficient in data reduction, length of the difference component words is adaptively determined according to their instantaneous amplitudes. This approach is low in both computational and hardware complexity, which introduces it as an attractive suggestion for high-density neural recording brain implants. Applied on multi-channel neural signals intra-cortically recorded using 16 multi-electrode array, the data is reduced by around 48%. Designed in TSMC 130-nm standard CMOS technology, hardware implementation of this technique for 16 parallel channels occupies a silicon area of 0.06 mm2, and dissipates 6.4 μW of power per channel when operates at VDD=1.2V and 400 kHz.Clinical Relevance- This paper presents a lossless data reduction technique, dedicated to brain-implantable neural recording devices. Such devices are developed for clinical applications such as the treatment of epilepsy, neuro-prostheses, and brain-machine interfacing for therapeutic purposes.
... Such an observation about the statistics of neural spiking provides an opportunity to design a very efficient neural interface. This data explosion problem relates to most BMI applications and researchers have investigated a wide range of options to address it, such as on-chip spike sorting [56], on-chip compression [57][58][59], compressive sensing [60], and active analog multiplexing [61][62][63] The electrical recording approach we propose performs lossy compression in the mixed-signal domain (i.e. before full digitization), exploiting two principles [64]. ...
Brain-machine interfaces (BMIs) of the future will be used to treat diverse neurological disorders and augment human capabilities. However, to realize this futuristic promise will require a major leap forward in how electronic devices interact with the nervous system. Current BMIs provide coarse communication with the target neural circuitry, because they fail to respect its cellular and cell-type specificity. Instead, they indiscriminately activate or record many cells at the same time and provide only partial restoration of lost abilities. A future BMI that may pave the path forward is an artificial retina—a device that can restore vision to people blinded by retinal degeneration. Because the retina is relatively well understood and easily accessible, it is an ideal neural circuit in which to develop a BMI that can approach or exceed the performance of the biological circuitry. This chapter summarizes the basic neuroscience of vision, identifies the requirements for an effective retinal interface, and describes some of the necessary circuits and systems. Based on these ideas and the lessons from first-generation retinal prostheses, a novel neuroengineering approach is proposed: the first BMI that will interact with neural circuitry at cellular and cell-type resolution.
... Reference [31] has proposed Pierson distribution as an appropriate distribution for circuit delay but this distribution has again four parameters and it takes a lot of time to estimate the delay in complex circuits. In the recent years, the most of the researchers claim that normal (gaussian) distribution is appropriate function for delay estimation [32][33][34][35][36][37][38][39][40][41][42][43][44][45]. ...
The process of modern integrated circuit (IC) design has been challenged by many factors. One of the most important challenges is the variation of device and circuit parameters during the manufacturing process. In this paper, the effects of manufacturing process variations on the gate delay have been modeled and an accurate yet low-cost simulation method for estimation of the circuit performance has been proposed. This additive method takes advantage of a 3-parameter probability density function (PDF), known as Burr distribution, to estimate the delay of each gate on the critical path. In this work, it is demonstrated that our proposed method is more accurate than previously proposed methods by taking into account the skewness of delay PDF. Although our proposed method is based on a 3-parameter PDF, we demonstrate that the simulation cost of our proposed method is no more than the conventional 2-parameter Gaussian PDF. We have compared the accuracy of our proposed method against the HSPICE simulation results. Moreover, we have compared the accuracy of our method with the most recent works with a 2-parameter PDF. The results for ISCAS85 benchmark circuits in our work have shown for 99 percentile points with average errors of 3.62, 3.49 and 2.78% in 90 nm, 45 nm and 22 nm technologies respectively.
This work presents an automatic and robust algorithm for surface electromyography signals segmentation in dynamic experimental protocol. The signals are segmented based on the peak burst occurrence. The two-dimensional array is constructed and used as input of a 2D signal encoder. The two-dimensional matrix lines may be long enough to have several bursts. The algorithm includes, besides segmentation modules, several others to eliminate the occurrence of false positives. An encoder that combines the AV1 and JPEG2000 toolset is used to compress data. Basically, depending on the target compression rate the encoder uses AV1 or JPEG2000. Examples of segmentation for electromyography signals digitalized from lower and upper limbs are shown. Data compression results for real electromyography signals data bank are presented. A performance comparison with other works reported in the literature is also included.
Neural interfaces of the future will be used to help restore lost sensory, motor, and other capabilities. However, realizing this futuristic promise requires a major leap forward in how electronic devices interface with the nervous system. Next generation neural interfaces must support parallel recording from tens of thousands of electrodes within the form factor and power budget of a fully implanted device, posing a number of significant engineering challenges. In this paper, we exploit sparsity and diversity of neural signals to achieve simultaneous data compression and channel multiplexing for neural recordings. The architecture uses wired-OR interactions within an array of single-slope A/D converters to obtain massively parallel digitization of neural action potentials. The achieved compression is lossy but effective at retaining the critical samples belonging to action potentials, enabling efficient spike sorting and cell type identification. Simulation results of the architecture using data obtained from primate retina
ex-vivo
with a 512-channel electrode array show average compression rates up to
$\sim$
40× while missing less than 5% of cells. In principle, the techniques presented here could be used to design interfaces to other parts of the nervous system.
