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In modern VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital converter (ADC) in 45nm CMOS technology is presented for low...
Citations
... Selecting TIQ comparators from the linear part of the threshold curve would keep DNL and INL values stable over VTC variation. Guha et al. in [7] and Khot et al. in [11] have fixed the NMOS transistor's were not reported to measure the efficiency of their selection method. Mishra and Nagar in [18] gathered the 15 TIQ comparators threshold voltages for their 4-bit flash ADC by fixing the width W N of the NMOS transistor to 4 µm and varying the width W P of the PMOS transistor to get the first 8 TIQ comparators voltages and reversed the process to get 7 more TIQ comparators. ...
In this work, we propose a novel procedure to generate and select threshold inverter quantized (TIQ) comparators for TIQ Flash ADCs. The new procedure generates more TIQ comparators than the procedure designed by Lee , Yoo, and Choi (LYC) (Proceedings of International Symposium on Quality Electronic Design, 2002). Two 6-bit TIQ Flash ADCs were designed, the LYC flash ADC, which selects its TIQ comparators using the current threshold selection algorithm, and the AC TIQ Flash ADC, which selects its TIQ comparators using the threshold selection algorithm proposed herein. Both ADCs were designed in \(0.5\,{\upmu }\hbox {m}\) CMOS technology and compared against the process, voltage source, and temperature (PVT) variations. Proposed TIQ selection procedure allows the designer to select the optimum TIQ set for desired ADC. AC ADC has a DNL values ±0.015 LSB and INL values between \(\pm 0.0225\) compared to ±0.1 LSB and 0.3 to −0.1 LSB for DNL and INL values of the LYC ADC. ENOB and SNDR for the AC were improved by at least \(31.3\%\) compared to LYC ADC, at typical process settings. For process, voltage source, and temperature (PVT) variations, in overall the AC ADC has at least better the DNL values by at least \(22.5\%\) and reduced INL values by at least \(35\%\). Over PVT variation, AC ADC has maintained ENOB value greater than 5.3 bits for all 16 variation corners. ENOB was improved by at least 1.5 bits over all corners. SNDR and SFDR were increased by at least 4 dB over the PVT corners. Proposed AC procedure shows scalability feature by generating extra threshold points for the \(65\hbox {-nm}\) TIQ comparators.
... New methods and approaches are being constantly developed in order to enhance the performance of ADCs [6]. Among the various types of ADCs, the flash ADC is the best, not only renowned for its data conversion rate, but also as a component in other ADCs, such as the pipeline and multi bit Sigma Delta ADCs [7]. ...
Analog signal is characterized by the signal whose amplitude is continuously changing with respect to time while the amplitude and time is discrete in case of signal. The existing system describes the design of FLASH ADC using clocked digital comparator (CDC) will leads to setup and hold time violation and consumes power. The proposed system use latch based digital comparator with level based which reduces the power and increases the speed. ADC is controlled by a pull down network which triggers selected ADC as per the selection logic. The length of transistor is fixed and depending upon the width of transistor, internal references voltages are generated in the range of 0.63 to 1.02V.The proposed 4-bit flash ADC using CDC is designed using multiplexer based decoder and simulated with the help of Tanner-EDA tool in Tsmc 0.18 cmos technology.
... Threshold Modified Comparator Circuit [1] had been developed again in the very next year to reduce power consumption in flash type ADC. In the same year, a SoC based low power 8-bit flash ADC in 45 nm CMOS technology had been designed in paper [4]. ...
Analog-to-Digital converters are useful components in signal processing and communication system. In digital signal processing low power and low voltage become a considerable component that are challenging for designing high speed devices and converters. The speed enhancement of serial links and the emerging communication technologies has inclined many researchers towards improvement of power and speed specifications. In this paper the implementation of a low power high speed 3-bit Flash Type ADC is being reported using 45 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the conventional comparator. While approaching for ADC we have designed a novel binary encoder and used it for low power design. The novel encoder based ADC consumes a very low power of 245nW.
The electronics world is faced with various challenges when attempting to integrate analog signals with discrete or digital systems. The ADC is not a new concept b y any means, but is still a topic of interest when it comes to technology due to its inevitable necessity in many systems being used today. Power consumption in ICs was always a challenging issue. Most of the technology emphasizes on speed, accuracy, less power consumption. In almost all digital functioning, encoders are mandatory. Decreasing power consumption in an encoder is an area of strong desire. In this paper, we have designed two novel ultra low power encoders for Flash ADC application and also show its comparison with previous encoder available in literature. The work has been done on Tanner tool v15 in 45 nm technology with various DC voltage supplies.
