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Source publication
In this paper, a new pure-digital frequency synthesizer Fout =(X/Y)∙Fin for square-waves with controlled precision is described. Given that Fin is the input reference frequency provided by a stable crystal oscillator, Fout is the synthesized frequency; X and Y are two co-prime integer numbers.
The purpose is to demonstrate that with exclusively si...
Contexts in source publication
Context 1
... architecture (Figure 1) is essentially composed of two readable/writable registers to store the X and Y co-prime integer numbers, an Up (C 1 ) and a Down (C 2 ) counter, an adder and a substractor, and a crystal oscillator that generates a stable standard frequency F c . A host-side-interface is also included to read/write the X & Y registers on the fly. ...
Context 2
... that F c is the master clock of the circuit (Figure 1). The actual maximal rate at which F c can run (F c _ Max ) depends on the physical characteristics of the chip, either ASIC or FPGA. ...
Context 3
... was achieved by using two simple-edge-triggered counters (C 1 duplicated), running respectively during opposite edges. When the F in /2N signal toggles (Figure 1), the accumulated results of the two counters are delayed one T c cycle in order to stabilize before being summed and then loaded into the C 2 counter. Such a trick simplifies the timing analysis of the architecture; otherwise it becomes more complicated as two types of clock-to-setup paths exist in the architecture: rising- to-falling and falling-to-rising F c edge paths. ...
