Figure 2 - uploaded by G. Cancelo
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Context 1
... configuration of the SVX3 chips are unique, and therefore, just the selected set of SVX3 chips should be configured. Figure 2 depicts the block diagram of the DDR chip. In Appendix A we have included the schematics ( Figure A.1). Next sections will specify and describe in detail the custom made chip for the PC. ...
Context 2
... FFs latches associated with the control lines of the SVX3 chips are also reset or preset as the result of the execution of the command sequence C[0:4]=16. The block diagram of the reset circuit is shown in Figure 2, while the details are shown in Figure A.1. ...
Context 3
... circuitry to perform this task is shown in details in Figure A.1 of the Appendix (also see the block diagram in Figure 2). When the control line BE_MODE of the SVX3 is set to "0", the "divide by two" circuit is selected by the multiplexer. ...
Context 4
... this situtation, both the IBE_CLK and the BE_CLK will be operating at 53 MHz. As previously observed, the BE_CLK also has circuitry to enable and disable the front end clock (see Figure A.1 of the Appendix and block diagram in Figure 2). This is accomplished through the DDR command code C[0:4] = 29, BE_CLK_EN. ...
Context 5
... the OBDV signal is asserted by several SVX3 chips in a chain, each SVX3 chip has the capability to assert and tri-state these lines in a specific sequence. This sequence is controlled by the 26.5 MHz BE_CLK and the TN line and is depicted in Figure 12. For more details on this protocol, see reference [7]. ...
