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We prove that MSO on $\omega$-words becomes undecidable if allowing to quantify over sets of positions that are ultimately periodic, i.e, sets $X$ such that for some positive integer $p$, ultimately either both or none of positions $x$ and $x+p$ belong to $X$. We obtain it as a corollary of the undecidability of MSO on $\omega$-words extended with...
We study the expressive power of successor-invariant first-order logic, which is an extension of first-order logic where the usage of an additional successor relation on the structure is allowed, as long as the validity of formulas is independent on the choice of a particular successor. We show that when the degree is bounded, successor-invariant f...
Citations
... The design of an arithmetic logic unit (ALU) using reversible logic gates is reported to minimize power dissipation in. [16] The binary full adder design1 and design2 are reported in. [17] In the field of IC design, minimum power dissipation design has emerged as a promising research area. ...
Arithmetic primitives are necessary in order to conduct computations on large numbers in arithmetic circuit implementations including multiplications, additions , subtractions, and divisions. Because of the importance of computations in the central processing unit, effective design of arithmetic circuit has been part of the most important fields of research for design engineers. In order to create low-power and energy-efficient portable processors for image and digital signal processing, as well as cryptography applications, the switching activity factor and cell count must be reduced. This research focuses on the reversible digital full adder circuit, which is a key element in establishing the Energy Delay Product (EDP) for various computer applications. Here, a new reversible binary full adder is designed using the switching activity concept and the logic decomposition method. The internal blocks for reversible full adders such as Feynman Gate, Toffoli Gate, and New Gate are designed first, then a new reversible binary full adder is developed using the proposed method. In this paper, conventional and proposed reversible full adders are synthesized using the Xilinx Vivado design suite for the Zynq-7000 family of device configuration. According to the implementation results, the proposed reversible full adder circuit consumes less dynamic power dissipation than the existing method in comparison. Furthermore, a formulae-based evaluation is conducted on the implementation results to estimate the EDP of the design. The proposed reversible full adder design can achieve a 32.3% EDP improvement compared to the Proposed Full Adder.
... The quantum cost of proposed circuit is undefined. Two ALU architectures are proposed based on Fredkin, Universal Reversible, Feynman, Toffoli and Peres Full adder gates [11]. The proposed circuit performs limited operations yet quantum cost is too high. ...
Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.
