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Bit-error-rate (BER) results for the LDPCCCs with different sizes. The results are obtained from FPGA experiments under AWGN channels and 4-bit quantization.
Source publication
This paper propose a decoder architecture for low-density parity-check
convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a
quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure,
the proposed LDPCCC decoder adopts a dynamic message storage in the memory and
uses a simple address controller. The decoder ef...
Context in source publication
Context 1
... observe from Table I that the LDPCCC using z = 1024 and I = 12 has a similar complexity with the ones using (i) z = 422 and I = 18 or (ii) z = 512 and I = 18. Figure 8 shows that the LDPCCC using z = 1024 and I = 12 is outperformed by the ones using (i) z = 422 and I = 18 or (ii) z = 512 and I = 18, even though the latter two codes have smaller sub-matrix sizes. It is therefore obvious that a larger number of decoding iterations can help reducing the error rate even when a smaller sub-matrix size is used. ...
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Citations
... Implementing LDPC codes, especially QC-LDPC codes onto FPGAs or application-specific integrated circuits (ASICs), are very common today. Comprehensive studies [11]- [13] have been conducted to reduce the complexity and improve the accuracy and throughput of the QC-LDPC decoders, such as applying appropriate calculations [14]- [17] and different structures of LDPC codes [18]- [20]. All the aforementioned studies adopt FPGAs or ASICs as their testing platforms in order to parallel and pipeline their decoding algorithm to the best extent. ...
With the emergence and popularity of iris biometrics, there are increasing concerns regarding the feasibility of iris authentication systems and their corresponding variability reduction methods. The former issues are typically addressed by optimizing key factors, such as iris size, image quality and acquisition wavelength. As for the latter, introducing error correction codes to reduce intra-user variability in the enrolled identifiers becomes novelly promising. This paper proposes a conventional iris authentication system and a hardware-friendly QC-LDPC error correction code scheme on a microprocessor-FPGA platform. Different QC-LDPC codes in IEEE 802.16e were analyzed and selected. Suitable codes were applied, followed by the evaluation experiments. The proposed design achieves a competitive result with up to 0.20% EER and 0.50% ZeroFAR on the CASIA-IrisV4-Syn database. Cryptographic keys with lengths of up to 288 bits can also be generated and recovered. Such a device can be potentially used for applications such as an access control system in high-security areas, identity verification at the borders, biometric cryptography and related authentication scenarios.
... B INARY low-density parity-check (LDPC) codes [1] [2] have become popular in recent years and have been adapted in 5th generation (5G) communication because of their near-capacity performance and hardware-friendly characteristics. In addition, there has been a significant development in binary LDPC decoders in the last few years [3] [4]. Although great success has been achieved in binary LDPC codes, they have a weakness in error correcting performance when using short code length. ...
... Fig. 18(a) shows the forward-backward stage for the proposed configurable ECN architecture. In order to efficiently use all the storage space in the FIFOs in the configurable design, we divide the FIFO S i (j), i ∈ [1,4], as shown in Fig. 16, into four FIFO segments S ik (j), k ∈ [1,4], as shown in Fig. 18(a). Also, three additional minimum operations need to be added. ...
... Fig. 18(a) shows the forward-backward stage for the proposed configurable ECN architecture. In order to efficiently use all the storage space in the FIFOs in the configurable design, we divide the FIFO S i (j), i ∈ [1,4], as shown in Fig. 16, into four FIFO segments S ik (j), k ∈ [1,4], as shown in Fig. 18(a). Also, three additional minimum operations need to be added. ...
Short non-binary (NB) low-density parity-check (LDPC) codes provide excellent error rate performance compared to their binary counterparts. This paper presents an efficient layered decoder architecture for short high-order non-binary LDPC codes. A hardware-friendly message-adaptation extended Min-Sum (MA-EMS) algorithm is proposed, where a variety of truncation sizes and message compressions are used, such that the number of decoding cycles and the storage requirements can be reduced. A configurable design that supports a variety of truncation sizes is also proposed such that the hardware efficiency can be significantly increased. An early termination (ET) scheme is used so as to decrease the required number of decoding cycles. These techniques can greatly reduce the complexity of the decoder with almost no loss in performance. To demonstrate these techniques, a (64, 32) 256-ary LDPC decoder is implemented in a 90 nm process, which can provide a throughput of 322.9 Mbps and occupies an area of 6.74 mm2. The proposed MA-EMS decoder is able to achieve a similar error-rate performance and a much better area efficiency compared to the original EMS decoder.
... Supposing we have retrieved N h values for {L PVN ch (β)} or {L PVN app (β)}, we need to interleave them -a process similar to that used in QC-LDPC decoding [33]. For each layer, the exact connections between the H-CNs and the P-VNs are determined by the CPMs, and hence the ...
Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of $1.48$ Gbps is achieved with a bit error rate (BER) of $10^{-5}$ at around $E_b/N_0 = - 0.40$ dB. The decoder can also achieve the same BER at $E_b/N_0 = - 1.11$ dB with a reduced throughput of $0.20$ Gbps.
... We denote the log-likelihood-ratio (LLR) values corresponding to P (t) by L P ch (t) and the LLR values corresponding to D(t) by L D ch (t). We consider a pipeline decoder which consists of I identical message-passing processors [23], [34], [33]. Each processor is a PLDPC-Hadamard block sub-decoder corresponding to [H W H W −1 · · · H 0 ]. ...
... For j = 1, 2, . . . , nL, compute(33) if b TDC (i, j) > 0; otherwise set I ev (i, j) = 0.Taking the first row of the 9 × 8 protomatrix B SC−PLDPCH−TDC in (31) as an example, we obtain the 1 × 8 vector b TDC (1, :) shown in(34). After analyzing the MI of the P-VNs, thecorresponding 1 × 8 MI vector I ev (1, :) is shown in (35). ...
In this paper, we propose a new type of ultimate-Shannon-limit-approaching codes called spatially coupled protograph-based low-density parity-check Hadamard convolutional codes (SC-PLDPCH-CCs), which are constructed by spatially coupling PLDPC-Hadamard block codes. We also develop an efficient decoding algorithm that combines pipeline decoding and layered scheduling for the decoding of SCPLDPCH- CCs. To estimate the decoding thresholds of SC-PLDPCH-CCs, we first propose a layered protograph extrinsic information transfer (PEXIT) algorithm to evaluate the thresholds of spatially coupled PLDPC-Hadamard terminated codes (SC-PLDPCH-TDCs) with a moderate coupling length. With the use of the proposed layered PEXIT method, we develop a genetic algorithm to look for good SC-PLDPCH-TDCs in a systematic way. Subsequently, we extend the coupling length of these SC-PLDPCH-TDCs with good thresholds to form good SC-PLDPCH-CCs. Based on the same set of split protomatrices, we regard the threshold of SC-PLDPCH-TDC as the proxy of SC-PLDPCH-CC when the SC-PLDPCH-TDC with long coupling length has almost the same code rate as the SC-PLDPCH-CC. Results show that our optimized SC-PLDPCH-CCs can achieve comparable thresholds to the block code counterparts. Simulations also illustrate the superiority of the SC-PLDPCH-CCs over the block code counterparts in terms of error performance. Moreover, for the rate-0.00295 SC-PLDPCH-CC, a BER of 1e-7 is achieved at Eb/N0 = -1.45 dB, which is only 0.14 dB from the ultimate Shannon limit.
... However, for code lengths greater than 500 bits, LDPC performance starts to dominate. In other studies, quasi-cyclic LDPC convolutional codes (QC-LDPC-CC) and spatially coupled LDPC convolutional codes were evaluated in [4,5]. Both studies showed improvement in latency and BER. ...
This paper presents a novel IEEE 802.16e (WiMAX) based decoder that performs close to the 5G code but without the expensive hardware re-development cost. The design uses an extension of the existing WiMAX parity check code to reduce the initial decoding latency and power consumption while keeping the decoder throughput at maximum. It achieves similar Frame Error Rate (FER) compared to 5G (0.1 dB off), and most notably the error curves trend down like 5G instead flooring. At FER= 10−3 there is 0.1 dB gain in the FER code performance compared to WiMAX. An implementation of the design is a modified version of the existing fully-parallel WiMAX decoder that supports multi-rate codeword size and reduces the initial latency by 33%. Additionally, for SNR greater than 3 dB, decoding only the shorter code reduces the power consumption by 34%.
... Low-density parity-check (LDPC) codes [11], [12] are one of error correction codes which can be used to handle the errors in an error-prone communication channel. There have been comprehensive studies [13]- [15] on improving the complexity and accuracy of the LDPC decoders in communication fields such as applying appropriate calculations [16]- [19] and different structure of LDPC codes [20]- [22]. ...
Extracting and analyzing iris textures for biometric recognition has been extensively studied. As the transition of iris recognition from lab technology to nation-scale applications, most systems are facing high complexity in either time or space, leading to unfitness for embedded devices. In this paper, the proposed design includes a minimal set of computer vision modules and multi-mode QC-LDPC decoder which can alleviate variability and noise caused by iris acquisition and follow-up process. Several classes of QC-LDPC code from IEEE 802.16 are tested for the validity of accuracy improvement. Some of the codes mentioned above are used for further QC-LDPC decoder quantization, validation and comparison to each other. We show that we can apply Dynamic Partial Reconfiguration technology to implement the multi-mode QC-LDPC decoder for the iris recognition system. The results show that the implementation is power-efficient and good for edge applications.
... The throughput of the dual-diagonal architecture is approximately inverse proportional to the row number of the base matrix. The architectures of the QC-LDPC decoder include: block parallel [16]- [18], row parallel [19], [20], full parallel [21], [22], etc. [23]. In 5G NR, the block parallel architecture is usually used to reduce the complexity of the decoder. ...
... From (22), we see that µ can be easily obtained from the fields already exist in the configuration and b † . From (23), we see that ν can be easily obtained from the fields already exist in the configuration and µ. As a result, only b † needs to be added to the configuration to indicate the sub-base matrix P m . ...
... From (22), we see that µ ∪ µ can be easily obtained from b ‡ since B can not be pruned. From (23), we see that ν ∪ ν can be easily obtained from the fields already exist in the configuration and µ ∪ µ . As a result, only b ‡ needs to be added to the configuration to indicate the sub-base matrix P m . ...
Quasi-cyclic low-density parity-check (QC-LDPC) codes are the choice for data channels in the fifth generation (5G) new radio (NR). At the transmitter side, code bits from the QC-LDPC encoder are delivered to the rate matcher. The task of the rate matcher is to select an appropriate number of code bits via puncturing and/or repetition. Code bits that are not selected do not need to be encoded. At the receiver side, the de-rate matcher combines code bits of different transmission attempts and sends them to the QC-LDPC decoder. The output of the QC-LDPC decoder only needs to include necessary systematic bits. Unnecessary systematic bits and parity bits can be completely removed from the decoding process. Taking these considerations into account, a smaller sub-base matrix instead of a full-base matrix can be used in the encoding and decoding process. In this paper, we propose an efficient implementation of QC-LDPC codes for 5G NR. The full-base matrix is pruned before being used. Compared to the traditional schemes, the proposed scheme improves the throughput of QC-LDPC codes in 5G NR.
... The good performance of SC-LDPC codes at low BER range compared with polar codes, another capacity-achieving code, have been validated using an FPGA-based simulation [7]. More construction methods with hardware implementation architecture were proposed for this specific type of code in [8,9]. ...
In this paper, we propose a unified field-programmable gate array (FPGA) structure for a rate-adaptive forward error correction (FEC) scheme based on spatially coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes. We described the unified decoder structure in detail and showed that the rate adaptation can be achieved by a controller on-the-fly. By FPGA based emulation, the results show that, with comparable complexity, the SC codes provide larger coding gain. The implemented unified structure can be employed for any template QC-LDPC code to achieve a spatially-coupling based code-rate adaptation scheme.
... In order to satisfy the strict error correction performance for some applications, the MS algorithm is sometimes not preferable. A SPA-based layered architecture was proposed then [12], [13]. Based on their experimental results, SPA-based architecture can achieve a better BER performance with reasonable logic complexity compared to MS-based architecture. ...
... To facilitate the discussion, a short review of how an original Block Processing Unit (original BPU) look like and run in a LDPC decoder is provided according to [13] [12]. Based on this original one, a V1 and V2 BPU will be presented afterwards. ...
... Building a look-up table (LUT) for a complex mathematical function can simplify the work that should have be done by following an algorithm and calculating the value. Previous Fig. 4. The V2 architecture of a BPU work [13] has adopted the look-up table approach to solve the impractical calculation of Sum-Product Algorithm. Their CNPs require Sign-and-Magnitude (SM) as the input data type but 2's-complement (2C) as output data type. ...
... Taking advantage of the convolutional coding structure, LDPC-CC also inherits the continuous encoding/decoding advantage from CC. As a result, both highly paralleled BP and Viterbi algorithms can be applied to reduce the decoding latency [89], [90]. Recently, a variant of LDPC-CC codes, i.e., spatially-coupled LDPC codes have attracted much attention due to their excellent asymptotic properties [91], [92]. ...
... Synthesis results have shown that the throughput can reach to 41 Gbps at clock frequency of 450 MHz [84]. For a LDPC-CC code with packet length of 422 bits and code rate of 5/6, the FPGA implemented decoder can provide 2-Gbps throughput with a clock frequency of 100 MHz, and has been demonstrated without error floor at BER of 10 −13 [89]. BER comparison in Fig. 10 also shown that, with the same code rate and packet length, LDPC-CC performs better than quasi-cyclic LDPC codes. ...
Demanded by high-performance wireless (WirelessHP) networks for industrial control applications, channel coding should be used and optimized. However, the adopted coding schemes in modern wireless communication standards are not sufficient for WirelessHP applications, in terms of both low latency and high reliability. Starting from the essential characteristics of WirelessHP regarding channel coding, this paper gives a detailed analysis of currently used short packet coding schemes in industrial wireless sensor networks (IWSNs), including seven coding schemes and their possible variants. The metrics employed for evaluation are bit error rate, packet error rate, and throughput. To find suitable coding schemes from a large number of options, we propose four principles to filter the most promising coding schemes. Based on overall comparison from the perspective of practical implementation, challenges of the available coding schemes are analyzed, and directions are recommended for future research. Some reflections on how to construct specially designed coding schemes for short packets to meet the high reliability and low latency constraints of WirelessHP are also provided.
