Fig 5
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This chapter focuses on analog layout process retargeting. Unlike automatic placement and routing tools, retargeting starts with an input layout in 6 a given process. The main target is to conserve most of the layout physical intelli- gence while migrating it to another given technology. This is usually achieved by adapting existing layout compacti...
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Citations
... Procedural generators can be based on a language or symbolic, and each cell has its own description. Recompaction, as used in [11,13,16,17], makes use of a generic tool to migrate existing cell layouts to a new fabrication technology or to improve its characteristics (as for yield optimization, OPC and DFM). Cell synthesis tools [1,4,6,11,14,28,42,45] generates layouts from a transistorlevel netlist description (as SPICE). ...
Integrated circuits implemented with traditional standard cell approaches use a limited set of cells available in a library, created in advance, to generate its layout. This approach breaks complexity but frequently generate circuits with more transistors (due to the reduced numbers of functions and sizes available), more area, higher delays and more power consumption (mainly due to static power consumption, which is proportional to the number of transistors) than its potential. Many approaches has been attempted to improve this scenario at layout level: cell synthesis tools (to speed up the turnaround time of new especially highly optimized special purpose cells), libraryfree layout synthesis and full custom layouts. We present in this paper a review the methodologies and algorithms used in prior works for transistorlevel layout synthesis, in especial recent ones targeting technologies beyond 65nm.
... There are many works in this field that failed in providing an e cient layout compaction method compatible with recent technology nodes [2,9,10]. Moreover, our methodology can also be applied to other problems like re-targeting/migration of digital [7] and analog [13] cells. ...
This paper describes a technique to compact cell layouts efficiently using Mixed-Integer Linear Programming. By using binary variables we were able not only to model the conditional design rules, which apply to technology nodes down to 65nm, but also to compact layouts in the two-dimensions simultaneously. This technique was applied to a transistor network layout synthesis tool called ASTRAN which is being used to generate on-demand cells with unrestricted transistor network structure. We demonstrate in this paper that our technique is able to generate dense cell layouts, competitive with manually designed cells.
... plexity of layout generation is increasing, which demands new techniques for the generation of dense layouts. Previous works with layout migration [3,9] and cell synthesis [4,5,10] do not support layout generation for newer technology nodes bellow 130nm. Celltk [6] supports 90nm but presents a large area overhead compared to standard-cells. ...
As the foundries update their advanced processes with new complex design rules and cell libraries grow in size and com-plexity, the cost of library development become increasingly higher. In this work we present the methodology used in ASTRAN to allow automatic layout generation of cell li-braries for technologies down to 45nm from its transistor level netlist description in SPICE format. It supports non-complementary logic cells, allowing generation of any kind of transistor networks, and continuous transistor sizing. We describe our new generation flow which is currently being used to generate a library with more than 500 asynchronous cells in a 65nm process.
... Trabalhos anteriores sobre migração de leiaute (FU et al., 2009;SAID et al., 2011) e síntese de células (ZIESEMER; LAZZARI; IIZUKA, 2007;GURUSWAMY et al., 1997) não suportam geração para nodos de tecnologia abaixo de 130nm. CellTK (KARMAZIN; OTERO; MANOHAR, 2013) suporta até 90nm, mas utiliza um fluxo próprio sem utilizar standard cells. ...
... Grande parte dos compactadores são capazes de compactar o leiaute em apenas uma direção de cada vez (1D) (MARPLE; SMULDERS; HEGEN, 1988;GURUSWAMY et al., 1997;LAZZARI, 2007;ZIESEMER;IIZUKA, 2007;FU et al., 2009;SAID et al., 2011). Entretanto, existem alguns poucos trabalhos que reportam o uso de compactadores bi-dimensionais (2D) que realizam a compactação da altura e largura da célula simultaneamente (SHIGEHIRO et al., 1994;MARPLE, 2012). ...
... Uma revisão dos métodos de compactação pode ser encontrada em (BOYER, 1988). Compactadores baseados em grafos (FU et al., 2009;SAID;ABBAS;SHAHEIN, 2007) são os mais comumente encontrados. Neste método, os nós representam os elementos do leiaute ou bordas dos polígonos, e os arcos representam regras de desenho ou restrições de conexão entre os elementos/bordas. ...
Fluxo de síntese física baseado em standard cells tem sido utilizado na indústria e academia já há um longo período de tempo. Esta técnica é conhecida por ser bastante confiável e previsível uma vez que a mesma biblioteca de células, que foi devidamente validada e caracterizada, pode ser utilizada em diferentes projetos. No entanto, há uma série de otimizações lógicas e elétricas para problemas como: circuitos assíncronos, redução do consumo estático, SEU, NBTI, DFM, etc. que demandam a existência de células inexistentes em bibliotecas tradicionais. O projeto do leiaute destas células é usualmente feito a mão, o que pode dificultar a adoção e desenvolvimento de novas técnicas.
Neste trabalho foi desenvolvido uma ferramenta para síntese automática do leiaute de redes de transistores chamada ASTRAN. Esta ferramenta suporta geração de células irrestrita quanto ao tipo da rede de transistores, incluindo com lógica não-complementar. Através da utilização de uma nova metodologia para compactação do leiaute com programação linear mista com inteiros (MILP), foi possível compactar eficientemente as geometrias das células simultaneamente em duas dimensões, além de lidar com regras de projeto condicionais existentes em tecnologias abaixo de 130nm.
ASTRAN conseguiu obter ganhos de produtividade ordens de grandeza superior ao do desenho manual das células ao mesmo tempo que conseguiu produzir resultados com similar densidade de transistores as standard cells.
