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This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successf...
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... hardware module performs its processing independently except for an interaction that occurs once in a macroblock se- quence, and a exible pipeline can be built with a com- bination of the processing. Figure 6 indicates the basic protocol of data transfer. The protocol of \Request" and \Status" provides a simple handshake between the modules. ...
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We propose a flexible video CODEC system for super-high-resolution videos such as those utilizing 4k × 2k pixel. It uses the
spatially parallel encoding approach and has sufficient scalability for the target video resolution to be encoded. A video
shift and padding function has been introduced to prevent the image quality from being degraded when different active line
systems are connected. The switchable cascade multiplexing function of our system enables various super-high-resolutions to
be encoded and super-high-resolution video streams to be recorded and played back using a conventional PC. A two-stage encoding
method using the complexity of each divided image has been introduced to equalize encoding quality among multiple divided
videos. System Time Clock (STC) sharing has also been implemented in this CODEC system to absorb the disparity in the times
streams are received between channels. These functions enable highly-efficient, high-quality encoding for super-high-resolution
video. The system was used for the 6k × 1k video transmission of a soccer tournament and the 4k × 2k video recoding of SATIO
KIKEN orchestral concert.
This super high resolution (SHR) video codec system is based on a spatial image division and multiple stream output approach and is implemented with multiple MPEG-2 HDTV Codec LSI's. The encoder has two operation modes, a non-multiplexing mode, and a multiplexing mode. In the non-multiplexing mode, the encoder outputs four constant bit rate transport streams (CBR-TS's) for which it can use two channel-synchronization schemes, system time clock (STC) sharing and sync-marker. In the multiplexing mode, the encoder outputs one CBR-TS comprised of four variable bit rate elementary streams (VBR-ES's), where cooperative operation between the pre-encoder and main-encoder realize adaptive bit allocation between four channels. The encoder also has a video shift and padding function which reduces distortion caused by the image division. These functions enable high-efficiency, high-quality SHR video coding.
This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. This architecture consists of triple encoding cores, a decoding core, a multiplexer/de-multiplexer core, and several dedicated application-specific hardware modules with a hierarchical flexible communication scheme for high-performance data transfer. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multi-chip configuration. The VASA implements MPEG-2 video and system CODEC with generic audio CODEC interfaces. An LSI incorporating the architecture was successfully fabricated using the 0.13 μm eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multi-view/-angled live TV applications with a multi-chip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.
This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability. The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and is more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final embedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(14): 72–80, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10004
This paper proposes a real-time MPEG-2 software CODEC for full-duplex transmission applications, and evaluates its performance and usefulness. The CODEC consists of a high-speed encoder/decoder, an IP sender/receiver, and an error recovery controller. Each encoder/decoder is accelerated and optimized by exploiting fast algorithms and instruction-level parallelism. The IP sender/receiver combination achieves low delay owing to the direct translating of each elementary stream of video and audio into UDP/IP packets. The error recovery controller carries out simple but powerful error tolerance against packet loss over IP networks. This CODEC attains low delay of 99 ms (M = 1, N = 1) to 165 ms (M = 3, N = 3) including input, encoding, transmitting, decoding, and output delays, and maintains a normal frame rate of 30 fps (frames per second) and more than 20 fps even under a fairly heavy network load. It provides sufficiently good performance for use as a real-time full NTSC-size CODEC on a PC of at least 1.2-GHz CPU. © 2005 Wiley Periodicals, Inc. Syst Comp Jpn, 36(2): 33–41, 2005; Published online in Wiley InterScience (). DOI 10.1002/scj.20151
We propose a flexible video CODEC system for super-high-resolution
videos such as those utilizing 4k × 2k pixel. It uses the
spatially parallel encoding approach and has sufficient scalability for
the target video resolution to be encoded. A video shift and padding
function has been introduced to prevent the image quality from being
degraded when different active line systems are connected. The
switchable cascade multiplexing function of our system enables various
super-high-resolutions to be encoded and super-high-resolution video
streams to be recorded and played back using a conventional PC. A
two-stage encoding method using the complexity of each divided image has
been introduced to equalize encoding quality among multiple divided
videos. System Time Clock (STC) sharing has also been implemented in
this CODEC system to absorb the disparity in the times streams are
received between channels. These functions enable highly-efficient,
high-quality encoding for super-high-resolution video.
This paper proposes a distributed stream multiplexing architecture for CODEC LSIs with multi-chip configuration, and demonstrates its scalability and usefulness. It consists of each media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip output at the end of the chain. Dispensing with external stream handling devices contributes to both high throughput and downsizing. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV channels. The architecture was implemented in a fabricated single-chip MPEG-2 422P@HL CODEC LSI and showed a good performance on an evaluation board system.
This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm×9.7 mm die using the 0.13 μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.
The vision of ambient intelligence opens a world of unprecedented experiences: the interaction of people with electronic devices is changed as contextual awareness, natural interfaces and ubiquitous availability of information are realized. We analyze the consequences of the ambient intelligence vision for electronic devices by mapping the involved technologies on a power-information graph. Based on the differences in power consumption, three types of devices are introduced: the autonomous or microWatt-node, the personal or milliWatt-node and the static or Watt-node. Ambient intelligent functions are realized by a network of these devices with the computing, communication and interface electronics realized in silicon IC technologies. Three case studies highlight the IC design challenges involved, and show the variety of problems that have to be solved.
Proposes a very small on-chip multimedia real-time operating
system (OS) for embedded system LSIs and demonstrates its usefulness on
MPEG-2 multimedia applications. The real-time OS, which has a new cyclic
task with `suspend' and `resume' for the interacting hardware/software
of embedded system LSIs, implements the minimum set of task, interrupt
and semaphore management on the basis of an analysis of embedded
software requirements. It requires only about 2.5 KBytes memory at
run-time, reduces redundant conventional cyclic task execution steps to
about 1/2 for hardware/software interactions and provides sufficient
performance in real time by implementing two typical embedded software
packages for practical multimedia system LSIs. This on-chip multimedia
real-time OS can be easily integrated on many embedded-system LSIs and
provides an efficient embedded software design environment
