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![FIGURE 1.7: DPL Gates Design [4]](profile/Ramzi-Jaber-2/publication/350963715/figure/fig4/AS:1014121101271040@1618796720681/DPL-Gates-Design-4_Q320.jpg)
![Fig. 1. Existing unary operators in Ref. [15]: A p , A n , A, A 0 , A 1...](profile/Ramzi-Jaber-2/publication/350963715/figure/fig40/AS:1014121113866244@1618796723250/Existing-unary-operators-in-Ref-15-A-p-A-n-A-A-0-A-1-and-A-2_Q320.jpg)
Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and en...
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... is done at 1 GHz operating frequency and room temperature at 27 • C as illustrated in Fig. 12 ...
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... comparison of the proposed TNAND demonstrates a notable reduction in PDP as shown in Fig. 12 (a). For Vdd=0.8 V, around 32.53%, 99.64%, and 90.07% compared to [13], [16], and [18] respectively. For Vdd=0.9 V, around 69.22%, 93.73%, and 94.35% compared to [13], [16], and [18] respectively. For Vdd=1 V, around 44.6%, 79.27%, and 98.3% compared to [13], [16], and [18] ...
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... is done at 1 GHz operating frequency, and power supply Vdd equals 0.9 V as illustrated in Fig. 12 ...
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... comparison of the proposed TNAND demonstrates a notable reduction in PDP as shown in Fig. 12 (b). For Temperature = 10 • C, around 60.88%, 94.09%, and 93.08% compared to [13], [16], and [18] respectively. For Temperature = 27 • C, around 69.22%, 93.73%, and 94.35% compared to [13], [16], and [18] respectively. For Temperature = 70 • C, around 61.34%, 90.13%, and 92.06% compared to [13], [16], and [18] ...
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... is done at power supply Vdd equals 0.9 V, and temperature equals 27 • C as illustrated in Fig. 12 ...
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... comparison of the proposed TNAND demonstrates a notable reduction in PDP as shown in Fig. 12 (c). For frequency = 0.5 GHz, around 71.46%, 94.18%, and 94.79% compared to [13], [16], and [18] respectively. For frequency = 1 GHz, around 69.22%, 93.73%, and 94.35% compared to [13], [16], and [18] respectively. For frequency = 2 GHz, around 61.27%, 92.23%, and 92.66% compared to [13], [16], and [18] respectively. Table 19 shows the ...
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... effect of temperature variation (from 0 • C to 70 • C) on the performance metrics of all proposed circuits is studied. Fig. 12 shows the comparison to the existing THA in Refs. [15][16][17] in terms of the average power consumption as shown in Fig. 12(a), maximum propagation delay as shown in Fig. 12(b), and maximum PDP as shown in Fig. 12(c) for a fixed frequency of 1 GHz, supply voltage of 0.9 V, and by varying the temperatures (from 0 • C to 70 • C). For ...
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... effect of temperature variation (from 0 • C to 70 • C) on the performance metrics of all proposed circuits is studied. Fig. 12 shows the comparison to the existing THA in Refs. [15][16][17] in terms of the average power consumption as shown in Fig. 12(a), maximum propagation delay as shown in Fig. 12(b), and maximum PDP as shown in Fig. 12(c) for a fixed frequency of 1 GHz, supply voltage of 0.9 V, and by varying the temperatures (from 0 • C to 70 • C). For Temperature = 10 • C, around 98.2%, 94.15%, and 93.66% compared to Refs. [15][16][17], respectively. For Temperature = 27 • C, ...
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... effect of temperature variation (from 0 • C to 70 • C) on the performance metrics of all proposed circuits is studied. Fig. 12 shows the comparison to the existing THA in Refs. [15][16][17] in terms of the average power consumption as shown in Fig. 12(a), maximum propagation delay as shown in Fig. 12(b), and maximum PDP as shown in Fig. 12(c) for a fixed frequency of 1 GHz, supply voltage of 0.9 V, and by varying the temperatures (from 0 • C to 70 • C). For Temperature = 10 • C, around 98.2%, 94.15%, and 93.66% compared to Refs. [15][16][17], respectively. For Temperature = 27 • C, around 98.45%, 94.39%, and 94.67% compared to Refs. ...
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... effect of temperature variation (from 0 • C to 70 • C) on the performance metrics of all proposed circuits is studied. Fig. 12 shows the comparison to the existing THA in Refs. [15][16][17] in terms of the average power consumption as shown in Fig. 12(a), maximum propagation delay as shown in Fig. 12(b), and maximum PDP as shown in Fig. 12(c) for a fixed frequency of 1 GHz, supply voltage of 0.9 V, and by varying the temperatures (from 0 • C to 70 • C). For Temperature = 10 • C, around 98.2%, 94.15%, and 93.66% compared to Refs. [15][16][17], respectively. For Temperature = 27 • C, around 98.45%, 94.39%, and 94.67% compared to Refs. [15][16][17], ...
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