Fig 2 - uploaded by Sri Chakrapani Yellamraju
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This paper proposes a design and implementation of high speed data transmission over dual independent aurora channels on One GTX (Gigabit Transceivers) DUAL TILE by configuring multi-gigabit transceivers (MGT's), which are present in the virtex-5 FPGA using aurora protocol. (Here GT means Gigabit transceivers (GT) and X indicates that these transce...
Citations
... The PCS of this standard was simulated by using Verilog HDL. Design and implementation of data transmission via dual independent aurora channels on one Gigabit transceiver on FPGA virtex-5 utilizing aurora protocol is proposed in [5]. 8b/10b encoding SerDes circuit is considered in [6], it was designed by XILINX Verilog. ...
This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.
In general , high data transfer rate of RADAR emitter would be a challenge for slow tracking devices. One of the solution to such problems, is adresssed in this paper. Data compression, by differential encoding technique facilitates to implement on available devices with less performance levels.
