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The recently adopted Ascon standard by NIST offers a lightweight authenticated encryption algorithm for use in resource-constrained cryptographic devices. To help assess side-channel attack risks of Ascon implementations, we present the first template attack based on analyzing power traces, recorded from an STM32F303 microcontroller board running W...
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Context 1
... that while Ascon AEAD allows arbitrary-length associated data and plaintexts, in this attack demonstration, we used empty associated data and 7-byte plaintexts, to keep the traces aligned and minimize their length when covering the entire encryption process. In other words, we focus entirely on the two invocations of permutation p 12 in the Initialization (KDF) and Finalization (TGF) phases, which process K. Figure 3 depicts this target encryption procedure. ...
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... to the lightweight structure of Ascon and our choice of short input size (Figure 3), it is practical to record power traces covering the full AEAD mode. Therefore, we built templates for target fragments of all the states α 0 , . . . ...
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... 7 shows the factor graph covering all the target states in our experiment. According to the encryption shown in Figure 3, the input state of the p 12 in Finalization will be the output state (or state β 11 ) of p 12 in Initialization, XORed with the state P (0x80)KK , where K is the key K with the least significant bit flipped. Therefore, via a constraint factor f ⊕ , the two variables, respectively representing the bit in the first lane L 0 of the input state of Finalization and its counterpart in the output state of Initialization, will be connected with the corresponding variable for the bit in the padded plaintext P (0x80). ...
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Citations
The arbitrarily connected nature of IoT has led to an explosion in the number of embedded devices accessed. These devices typically store and process large amounts of private and critical data. Most of these data are transmitted in plaintext over the bus, which is vulnerable to attacks such as theft, leakage, tampering, and even control flow hijacking. Encryption and authentication of memory data can effectively alleviate these problems. Existing solutions introduce significant performance overhead while providing data protection. Therefore, in this article, we propose a low-latency, high-performance transparent memory data encryption and authentication hardware protection scheme based on Ascon-128, in which the multistage pipeline design and the optimization of address labels effectively reduce the encryption/decryption latency and the size and storage overhead of nonce data. Based on the designed hardware architecture, the performance overhead introduced is evaluated in terms of bandwidth, latency, runtime, and score using multiple test programs on a CVA6-32-bit RISC-V SoC platform. The measured results from TinyMemBench demonstrate that the memory read and write bandwidth introduced by the proposed transparent memory data encryption and authentication scheme is reduced by 10.2% and 5.6%, respectively. For real intensive computational loads, the average runtime of Crystal-Dilithium and Crystal-Kyber increases by 6.32% and 6.42%, respectively, under three different parameter sets.
IoT devices and embedded systems are deployed in critical environments, emphasizing attributes like power efficiency and computational capabilities. However, these constraints stress the paramount importance of device security, stimulating the exploration of lightweight cryptographic mechanisms. This study introduces a lightweight architecture for authenticated encryption tailored to these requirements. The architecture combines the lightweight encryption of the LED block cipher with the authentication of the PHOTON hash function. Leveraging shared internal operations, the integration of these bases optimizes area–performance tradeoffs, resulting in reduced power consumption and a reduced logic footprint. The architecture is synthesized and simulated using Verilog HDL, Quartus II, and ModelSim, and implemented on Cyclone FPGA devices. The results demonstrate a substantial 14% reduction in the logic area and up to a 46.04% decrease in power consumption in contrast to the individual designs of LED and PHOTON. This work highlights the potential for using efficient cryptographic solutions in resource-constrained environments.
