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Artix-7 FPGA resource summary for REPC module

Artix-7 FPGA resource summary for REPC module

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Figure 2. Hardware architecture of REPC module
Field lengths used in REPC
Each stage output signals description
RBVE output generation for each stage
+1 Artix-7 FPGA resource summary for REPC module
Range-enhanced packet classification to improve computational performance on field programmable gate array
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  • Dec 2022
span lang="EN-US">Multi-filed packet classification is a powerful classification engine that classifies input packets into different fields based on predefined rules. As the demand for the internet increases, efficient network routers can support many network features like quality of services (QoS), firewalls, security, multimedia communications, a...
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... REPC architecture is modeled using Verilog-HDL on the Xilinx ISE environment and simulated using the Model-sim 6.5f simulator. The Hardware design constraints like chip area, time, power, Latency, and throughput are analyzed for REPC on Artix-7 FPGA and tabulated in Table 4. ...

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A high-performance dual classifier based packet classification engine on FPGA
Article
  • Jan 2023
Security is one of the key elements of real-time communication systems, especially with the developments in digital communication systems. One of the most crucial networking activities that guards against hacking and unintentional consequences on connected devices is packet classification. The router's and other linked devices' sluggish processing speeds are a problem for implementing real-time packet classification. This paper proposes a novel parallel architecture for packet classification in routers. The design that has been suggested uses the parallelism that modern hardware technologies offer to categorize several packets at once to increase throughput, lower energy usage, and drastically lower latency. The suggested design supports multiple data reads by utilizing Dual Port RAM, or DPRAM. They have low latency performance and allow for fast rate packet lookup, making them the preferable choice for stage memory. The DPRAM provides the data to the packet scheduling module. The packets are received concurrently by the two subsequent packet splitter units. The throughput of packet classification increases as a result. In this paper, a parallel packet categorization architecture using FPGA is explored for maximizing throughput and maintain allowable latency while preserving low energy consumption. The classifier has the lowest energy efficiency of 7.2nJ and less latency of 58 ns. Its throughput may reach 668 MPPS (million packets per second).
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