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The current trend in real-time operating systems involves executing many tasks using a limited hardware platform. Thus, a single processor system has to execute multiple tasks with different priorities in different real-time system (RTS) work modes. Hardware schedulers can greatly reduce event trigger latency and successfully remove most of the sch...
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... section describes the architecture of the hardware scheduler and its internal structure (see Figure 3). The real-time event handling unit is a scalable module based on the Mealy finite-state machine (FSM), which can be successfully used even in real-time applications. ...
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... sCPUiEvi signal, which is used to signal the occurrence of an expected event, is enabled by the stop_CPUi signal. The scheduler registertransfer level (RTL) equations are the following ("∧" AND logic, "∨" OR logic, "/" NOT logic, "CLK" HW_nMPRA_RTOS processor clock, "↑" positive edge trigger): The FSM outputs (Oi) are dependent on the scheduled sCPUi IDs and also on the current inputs represented by the events in Figure 3. ...
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... block diagram contains the sCPUi_ready functional blocks and the register that stores the ID of the highest priority sCPUi (see Figure 3). Subsequently, the AND gate and the D flip-flop are activated when there is no other active sCPUi. ...
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... the AND gate and the D flip-flop are activated when there is no other active sCPUi. The Figure 3 block shows the ID register of the active sCPU together with the synchronization logic, the static scheduler, the dynamic scheduler and the block related to the events. The en_CPU signal can be used mainly for power saving. ...
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... 10a illustrates the test performed for the practical measurement of the kernel latency corresponding to the nHSE scheduler (58.2 ns), i.e., the change in the output of the FSM states that generate the next transition through the nHSE_FSM_state[7:0] signals (time moment T2 from Figure 6). Thus, tests were run to confirm that the hardware scheduler has a jitter of 1 clock cycle plus the time needed to trigger the IntEvi event (signal ExtIntEv[0] external interrupt), but any of the events specified in Figure 3 can be triggered. In addition, Figure 10b shows the oscilloscope capture for measuring the time of the thread context switch in 1 clock cycle, where the second cursor measures the transition of the signal nHSE_Task_Select ( Figure 6). ...
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Citations
... Second, to extend the C-TPN modeling to cyber-physical systems [31] by explicitly specifying the communication network and the continuous aspects of environmental data variables. Third, to establish a development software methodology, e.g., in Java, based on C-TPN and the concepts of model continuity [31], that is, the possibility of transitioning, with minimal distortions, a source model onto a final custom implementation architecture [32]. Fourth, due to the uncertainty that unavoidably accompanies the correct prediction of the execution time of task actions (e.g., [5]), an important goal of the final real-time software is to possibly admit state degradation modes and abort decisions [33] with recovery means, so as to minimize the risks corresponding to a deadline miss. ...
Modeling and verification of the correct behavior of embedded real-time systems with strict timing constraints is a well-known and important problem. Failing to fulfill a deadline in system operation can have severe consequences in the practical case. This paper proposes an approach to formal modeling and schedulability analysis. A novel extension of Petri Nets named Constraint Time Petri Nets (C-TPN) is developed, which enables the modeling of a collection of interdependent real-time tasks whose execution is constrained by the use of priority and shared resources like processors and memory data. A C-TPN model is reduced to a network of Timed Automata in the context of the popular Uppaal toolbox. Both functional and, most importantly, temporal properties can be assessed by exhaustive model checking and/or statistical model checking based on simulations. This paper first describes and motivates the proposed C-TPN modeling language and its formal semantics. Then, a Uppaal translation is shown. Finally, three models of embedded real-time systems are considered, and their properties are thoroughly verified.
... This algorithm guarantees deadlines for tasks, which must provide a WCET and a real-time response to external stimuli. Figure 6 illustrates the MIPS32 [31] instructions executed by instP3 and instP0, as captured by the Vivado Design Suite simulator. The multiplication of each ID_Instruc-tion_reg[0:3][31:0] pipeline register, one for each HW_thread_i, can be seen as the basic idea of the nMPRA architecture, patented in Germany, Munich [32]. ...
Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the implementation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on synthesizing in field-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in different configurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper.
... Thus, we are considering in the future to develop an emulator for the HW_nMPRA_RTOS concept supporting RISC-V, MIPS32, and ARM ISA. The papers [7], [26], [27] present these simulations at the concept level and do not explain the algorithms underlying the implementation of the real-time scheduler. In [7] the basic concept of nMPRA is presented for the first time, with a static Round Robin scheduling. ...
... In [7] the basic concept of nMPRA is presented for the first time, with a static Round Robin scheduling. In [26] only a basic solution for handling mutex type events is presented. In the overview presented in [27] different ISAs for nMPRA processor support, namely MIPS32, RISC-V and ARM, are reviewed. ...
In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an FPGA-based development platform, through an SoC project, the implementation of HW_nMPRA_RTOS (a unified acronym for multi pipeline register architecture (nMPRA) where
n
is the degree of datapath resource multiplication, hardware scheduler engine (nHSE) for
n
threads and RTOS application programming interface (API)), dedicated processor architecture was developed, simulated and validated. This paper propose an innovative soft-core implementation to reduce interrupt latencies, while maintaining strong spatial and temporal isolation. Among the results which contain relevance and novelty, we can mention: rapid tasks context switching (1 clock cycle); The implementation of a distributed and versatile interrupt system which allows the interrupt attachment to any task; The implementation of a static scheduler and support for the dynamic tasks scheduling; Rapid response to events of up to 2 clock cycles. We demonstrate the architecture’s predictability, scalability, and performance by running a set of benchmark applications on several configurations of HW_nMPRA_RTOS synthesized on a Xilinx 7 Series FPGA.
One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.
