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As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the injected noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. In this paper, we...
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... demonstrate the noise-tolerance capability of the MRF circuits, we utilize an 8-bit carry-look-ahead adder (CLA) as a proof-of-concept design for performance comparison. The proposed 8-bit MRF CLA is illustrated in Fig. 4. To construct a MRF-CLA, we divide the whole CLA into many basic cells and map the MRF circuit on these basic cells. By this way, the design overhead will not increase rapidly and the noise-tolerance performance can be preserved. Both the probabilistic-based MRF CLA and the conventional deterministic CMOS CLA circuits are implemented ...
Citations
... Probabilistic approaches can be applied to different levels of abstraction, however, circuit-level ones are more effective and easier to implement [16]. Among various probabilistic frameworks like Markov random field, Bayesian network (BN), probabilistic transfer matrices (PTM) and probabilistic decision diagrams (PDD), Markov random field has received great attention for designing noise-tolerant VLSI circuits [13][14][15][16][17][18][19][20][21][22][23][24][25]. In MRF-based circuits, noise energy is shared among the whole system and noise signal level is reduced noticeably. ...
... Several MRF-based methods have been used for designing noise-tolerant circuits [13][14][15][16][17][18][19][20][21][22][23][24][25]. A straightforward method for mapping MRF design principles to VLSI circuits was proposed in [17,18] for the first time. ...
... Several MRF-based methods have been used for designing noise-tolerant circuits [13][14][15][16][17][18][19][20][21][22][23][24][25]. A straightforward method for mapping MRF design principles to VLSI circuits was proposed in [17,18] for the first time. Because of the hardware complexity of the initial MRF-based design, most of the methods which have been proposed focused on techniques for reducing hardware overhead. ...
The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circuits. First, excessive hardware overhead that imposes a great cost, power consumption, and propagation delay on the circuits, and second, separate implementation of feedback lines that adds further delay to the circuits. In this paper, we propose a novel approach for minimal-cost inherent-feedback implementation of low-power MRF-based logic gates. The simulation results, which are based on 32nm BSIM4 models, demonstrate that besides the excellent noise immunity of the proposed method, it has the least propagation delay in comparison with all of the previously reported MRF-based gates due to its inherent feedbacks. In addition, the proposed method outperforms competing ones, which have comparable noise immunity, in other circuit metrics like cost and power consumption. Specifically, the proposed method achieves at least 18%, 29%, and 39% reductions in cost, delay, and power consumption with considerable noise immunity improvement compared with competing methods.
... The first effort for mapping the MRF theory to the VLSI circuits design was accomplished in Ref. [18]. Soon after that, a similar approach was used to implement the first MRF-based chip [19]. After the introduction of the MRF-based circuits, several MRF-based methods have been proposed for designing reliable noise-tolerant VLSI circuits [20][21][22][23][24][25][26][27][28][29][30]. ...
... In this approach, all of the states are generated and fed back to the associated nodes. A similar method was used for the fabrication of an 8-bit carry-lookahead adder chip in Ref. [19] which its two-input NAND implementation is shown in Fig. 2a. For a two-input NAND gate, the valid states' function (the summation of the valid states) is F ¼ X0X1X2 þ X0X1X2 þ X0 X1X2 þ X0X1X2 which X0 and X1 are inputs and X2 is output. ...
... Two-input NAND versions of initial MRF-based designs (a) Straightforward approach[19] (b) Simplified approach[20]. ...
Noise-interference is one of the major concerns in low-power VLSI circuits. Due to power supply downscaling, these circuits have an extremely limited noise margin that is inadequate for dealing with intrinsic and extrinsic noise. The MRF-based design has been accepted as a highly effective method for designing noise-tolerant low-power circuits. However, the MRF-based circuits suffer from a complex structure and the methods which tried to simplify the structure always sacrificed the noise immunity for hardware simplicity. In this paper, we propose a novel MRF-based method for designing efficient and reliable low-power VLSI circuits. For the first time, an innovative reliability boosting mechanism based on maximum conditional correct probability is incorporated into an efficient MRF-based structure which leads to highly reliable circuits with considerably low cost, delay, and power consumption. The proposed method demonstrates the best performance among all of the previously reported methods. Moreover, the Monte Carlo simulations confirm that the proposed method can preserve its superior noise immunity even under serious process, voltage, and temperature variations.
... The original MRF-based circuit design is directly mapped from the MRF theory [2]. An 0.18μm eight-bit MRF carry lookahead adder was implemented to achieve 10 −6 Bit Error Rate (BER) under the supply voltage of 0.45V [3]. Since output signals are fed back to the corresponding MRF network based on all valid logic states, it requires significant hardware overhead due to the complexity of the MRF network. ...
... The MRF-based design [2] which has the best noise immunity costs about 14 times the area of the standard CMOS design. It is in line with the result in [3] that the original MRF design implemented using the 180 nm technology has much better noise immunity than the standard CMOS one at the cost of 14 times the chip area. It also indicates that the advantage of all MRF-based circuit designs having better noise immunity than non-MRF CMOS one is invariant to the applied technology even though the designs require a larger area and a longer delay. ...
Discrete Cosine Transform (DCT) is a commonly used building block for image and video compression. In this article, we present a Markov Random Field (MRF)-based design for DCT implementation because MRF logic gates outperform standard non-MRF units by achieving high noise immunity for applications to logic-based computing systems in deep sub-micron condition. Furthermore, it is found that stochastic logic, a low-cost form of number representation, can also efficiently simplify computations. By combining these two techniques, we present an improved DCT hardware circuit. The example eight-point one-dimensional DCT (1D DCT) system is simulated using 65 nm CMOS technology. Simulation results show that the proposed MRF design can achieve 13% higher noise immunity and 47% area saving, compared with the typical stochastic 1D DCT using classical Master-and-Slave architecture. While achieving the same error rate of 0.21, power consumption is reduced by 52%.
... However, there is no theoretical analysis for the supply voltage of MRF circuits. The authors in references [3][4][5] only proved the clique energy representations of basic elements, but did not explain clearly the reliability of MRF-based feedback structure in ultra-low supply voltage. ...
... By the construction, we can obtain the following representations 00 11 5 In this section, we prove three lemmas about the relationships between MRF approach and traditional approach for the output entropy, condition entropy and mutual information in the condition that they can achieve the same output correct probability. We also provide the method for the comparison of supply voltage between two approaches. ...
Reliability is an essential issue in circuits design. The methodology of Markova random field (MRF) provides a new way for ultra-low supply voltage design to obtain high noise-immune performance. However, MRF circuits have a lack of the analysis for the supply voltage. In this paper, we use information theory to analyze the low bound of the supply voltage. Then, we prove the MRF circuit has lower supply voltage compared to the traditional circuit under the same output correct probability. The contribution of this paper is providing a mathematical proof for MRF circuit from the information theory viewpoint in low supply voltage design.
... Recently, some design methodology based on generalized reliability analysis techniques are proposed for nano-scale circuits design. Markov random field (MRF) model was proposed initially in [18] and extended in [19, 20]. MRF was developed to support optimization of a set of random variables so that their overall joint probability is a global maximum. ...
As the transistor sizes continue to shrink, quantum effects will significantly affect the circuit behavior. The inherent unreliability of nano-electronics will have significantly impact on the way of circuits design, so defects and faults of nano-scale circuit technologies have to be taken into account early in the design of digital systems. Fault-tolerant architectures may become a necessity to ensure that the underlying circuit could function properly. In CAD software, a same logic can be made out with different circuits but different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the error rate of the circuit efficiently to make the design more fault tolerant. In this paper, a new way to fault tolerance design in nano-scale circuit by accurate soft error rate (SER) estimation is proposed. Transform matrix is used for SER computation and a design criteria is then proposed. Simulation results show that the proposed transform matrix model is effective for nano-scale circuits and the criteria delivered is suitable CAD tools development in nano-system design.
... Because intrinsic noise is random and dynamic in nature, conventional deterministic logic design methods used in CMOS circuits are insufficient to handle these faults. Probabilistic approaches are more desirable to handle this problem [1], [19]–[21]. In probabilistic-based noise-tolerant approaches, the noise energy is shared and averaged by the whole system; therefore , the noise signal level can be greatly reduced. ...
... A possible MRF circuit design was presented in [20] and [21], where the MRF theory was mapped onto logic circuits. An MRF silicon chip design was further presented in [1] to prove the design concept of noise-tolerant MRF circuits. As demonstrated in [1], [20], and [21], the probabilistically based circuits can achieve much better noise immunity than their CMOS counterparts. ...
... An MRF silicon chip design was further presented in [1] to prove the design concept of noise-tolerant MRF circuits. As demonstrated in [1], [20], and [21], the probabilistically based circuits can achieve much better noise immunity than their CMOS counterparts. However, the hardware overhead of MRF direct-mapping circuits in [1] is much larger than that of deterministically based CMOS circuits. ...
As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-mum CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a 7.00 times 10<sup>-5</sup> bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide 8.84 times 10<sup>-3</sup> BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 muW/MHz of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .
... In [1], a probabilistic noise-tolerant circuit design was proposed and implemented based on the theory of Markov Random Field (MRF) [2]. The MRF provides a formal probabilistic framework so that computation can be directly embedded in a network with immunity to both device and signal failures. ...
... By computing the logic states in a probabilistic way, the MRF-based noise-tolerant circuits can bring the circuit to operate with better noiseimmunity. However, the area overhead of MRF circuits in [1] is about 10 times larger than the conventional CMOS circuits. Therefore, in this paper, we propose a hardwareefficient probabilistic-based noise-tolerant circuit through MRF network simplification. ...
... The measurement results show that the proposed MRF_CLA can provide 24.5dB of noise-immunity enhancement as compared with the conventional CMOS CLA. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1]. ...
As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov random field carry lookahead adder (MRF_CLA), in 0.13 mum CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5 dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1].
... The challenges are to handle both hardware faults and signal faults simultaneously given that we have no prior knowledge when and where these faults might occur. In order to achieve this goal, the probabilistic-based model and circuit design are proposed: the Markov Random Field design [2], [10], [11]. ...
... The Markov random field (MRF) model was proposed initially in Ref. [2] and extended in Ref. [10] and [11]. MRF was developed to optimize a set of random variables so that their overall joint probability is a global maximum. ...
Abstract—Two probabilistic-based models, namely the Ensemble-Dependent Matrix ,model ,[1][3] and ,the Markov Random Field model [2], have been proposed to deal with faults in nanoscale system. The MRF design can provide excellent noise tolerance in nanoscale circuit design. However, it is complicated to be applied to model circuit behavior at system level. Ensemble dependent matrix methodology is more effective and suitable for CAD tools development and to optimize nanoscale circuit and system design. In this paper, we show that the ensemble-dependent matrices ,describe the ,actual circuit performances when signal errors are present. We then propose a new criterion to compare circuit error-tolerance capability. We also prove that the Matrix model ,and ,the Markov model converge when signals are digital
Probabilistic-based methods have been used for designing noise-tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in comparison with previous probabilistic-based methods is its ultra-high reliability. The proposed method benefits from the Markov random field (MRF) as a probabilistic framework and triple modular redundancy (TMR) as a reliability mechanism. A NAND gate is used to show the design methodology. The simulation results verify the noise immunity of the proposed MRF-based gate in the presence of noise. In addition, the values from the reliability estimation program show the reliability of 0.99999999 and 0.99941316 for transistor failure rates of 0.0001 and 0.001, respectively, which are much better as compared with previous reported MRF-based designs.
Reliability is one of the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques have been applied to logic circuits to resist random noise when operating under ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks can be easily mapped onto simple logic circuits, it becomes difficult when the circuits are large and complex. In this paper, we present a general coding-based partial MRF (CPMRF) method for multi-logic operations in one basic unit, which is referred to as a CPMRF pair. A CPMRF pair saves circuit area by sharing a common MRF network. It also inherits noise immunity from the MRF theory while obtaining noise immunity from the coding structure as a combination of robust "1s" and "0s." The resulting architectures become more cost effective than conventional ones. To validate the performance of our proof-of-concept design, we fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM 130-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20% improvement while occupying 37.7% less area and reducing power consumption by 93% compared with the master-and-slave MRF CLA design.
