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A multiplier is an essential component in high-performance systems including digital signal processors, arithmetic & logical units (ALU), and various other communication systems. The multiplication method essentially needs a lot of hardware resources and more computation time than the other arithmetic operations such as addition and subtraction. In...
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... an effort to enhance the overall working of the multiplier, certain modifications in the initial building blocks of architectural design are proposed. Fig. 7 illustrates the use of sixteen AND gates, six full adders, three half adders, with a special 5-bit adder for making an efficient multiplier architecture. A special 5-bit adder is designed such that it takes 5 bits of binary data and generates a 3-bit output. The internal architecture of a 5-bit adder (Fig. 8) comprises of two full ...
Citations
... The MIM is designed using two metal layers separated by one dielectric layer [15,16]. It is characterized by high light confinement and an acceptable propagation length [17][18][19][20]. The plasmonics structures are used to design several passive and active devices such as multiplexers/de-multiplexers, logic gates, hybrid plasmonic waveguides, Bragg reflectors, flip-flop circuits, combiners, splitters, switches, modulators filters, resonators, encoders/decoders, and multipliers [6,[21][22][23]. ...
The plasmonic 2-bit multiplier is designed at a 1310 nm operating wavelength and a 65% transmission threshold ( ${{\rm T}_{{\rm threshold}}}$ T t h r e s h o l d ). Using the finite element method (FEM) with the COMSOL version 15 software, we simulated the suggested 2-bit multiplier, based on the principle of the constructive and destructive interferences between the input light waves. The results were delivered in graphs containing the transmission level (T) versus an operating wavelength range between 800 and 2000 nm, magnetic field distribution, modulation depth (MD), contrast ratio (CR), and insertion loss (IL). The modulation depth was 99.91%, the CR was 14.75 dB, and the IL was ${-}{1.2}\;{\rm dB}$ − 1.2 d B .
... Among the various Vedic multiplication algorithms [6], the Urdhva Tiryakbhyam (UT) technique has gained significant attention for its ability to perform highspeed multiplication operations efficiently. This manuscript serves as an extension to the paper presented [7]. The proposed architecture in this study utilizes a novel 5-bit special adder, in conjunction with full adders and half adders, to implement a 4x4 multiplier based on the UT technique of Vedic mathematics. ...
... The final product is obtained in step 8 and results in 01101110 (decimal 110). [7]. Similarly, the basics of this sutra can be applied to higher-order binary multiplication. ...
... The proposed 4-bit Vedic multiplier architecture is depicted in Fig. 2 and the schematic representation is displayed in Fig. 3 This 4-bit VM is composed of 16 AND gates, 6 FAs, 3 HAs, and a 5-bit special adder-a circuit that accepts 5-bit binary data and provides a 3-bit output. These components are intelligently combined to create an optimized VM that enhances performance while minimizing power consumption [7]. To implement an 8-bit VM, four modules of the proposed 4bit Vedic multiplier are utilized, along with three 8-bit Ripple Carry Adders (RCAs) to perform the necessary additions and generate the final 16-bit output (Fig. 4). ...
