Architecture of the Scone System-on-Chip. 

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... these goals in mind, a hardware platform, based on the use of FPGAs (Field Programmable Gate Arrays) for fast reasoning under the Scone framework has been proposed. In Figure 1, a high level picture of the proposed reasoning hardware platform (from now on RHP) is depicted. The system is composed of the following elements: ...

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... a dynamic point of view, the proposed platform can freely grow avoiding an oversized initial configuration. If needed, a new SN can be instantiated in a free partial reconfiguration area (see white dotted box in Figure 1) in order to expand, for example, the semantic network with a new branch defining a subclass of the thing supernode. New entries can be added to the existing SNs through writing operations performed on local memories. ...

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... mentioned in previous sections, the marker-passing algorithm implemented by Scone is one of its main strengths. Briefly, the marker-passing mechanism is mainly devoted to extract the implicit knowledge that it is contained in the semantic network by means of propagating pieces of information through the complex web formed by nodes and links. Thus, three main challenges arise when facing the hardware implementation of such a kind of knowledge-base systems: (a) to simplify the representation and storage of the semantic network information; (b) to optimize the memory organization for a fast and efficient implementation of the marker-passing algorithm; and (c) to provide a scalable and distributed architecture that simplifies the task of adding new knowledge while at the same time being capable of performing parallel searches. Bearing these goals in mind, a hardware platform, based on the use of FPGAs ( Field Programmable Gate Arrays ) for fast reasoning under the Scone framework has been proposed. In Figure 1, a high level picture of the proposed reasoning hardware platform (from now on RHP) is depicted. The system is composed of the following elements: • A Microblaze processor running at a frequency of 125 MHz. There is no other operating system running in the platform but a little software layer ( Xilkernel ) implementing basic ...

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... device chosen for the implementation of this prototype is a XUPV5 board ( from Xilinx. It is based on a Virtex5 LX110T chip, equivalent to four million logic gates with run-time partial reconfiguration capability. Our reasoning hardware platform takes advantage of this dynamic feature provided by the FPGA in order to adapt itself to unforeseen scenarios while beings scalable. For example, the number of SNs instantiated in a given moment depends on the size of the semantic tree capturing the information for the application under execution. From a static point of view, unused SN instances are unnecessarily wasting power consumption. From a dynamic point of view, the proposed platform can freely grow avoiding an oversized initial configuration. If needed, a new SN can be instantiated in a free partial reconfiguration area (see white dotted box in Figure 1) in order to expand, for example, the semantic network with a new branch defining a subclass of the thing supernode. New entries can be added to the existing SNs through writing operations performed on local memories. The work proposed here resorts to the infrastructure for dynamic reconfiguration management for Xilinx platforms developed by Dondo et al . [22]. Another scenario that is worth being mentioned refers to the fact that it is possible to face a run-time rearrangement of the semantic tree data among the SNs. For optimization purposes (see Section 3.5) it would be necessary to split one branch of the semantic tree (actually stored in one SN) and consequently more SNs will be instantiated to hold the resultant subtrees. This section is aimed at presenting an overview of how the RHP works at system level, before getting into the implementation details of the individual Semantic Nodes. From the user’s perspective, the presence of the RHP is totally transparent since it is remotely used through the standard Scone ...