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A fully integrated direct-conversion tuner is implemented in 0.13 mum CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gai...
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... optimize noise, linearity and power consumption. To optimize noise, power consumption and silicon area, it is necessary to make trade-offs in the Op-amp together with the input/feedback resistor pair. In this design, the analog baseband provides total gain control from 0 to 63.5 dB in 0.5 dB steps. It includes several circuit blocks as shown in Fig. 7: a vari- able-gain low-pass channel filter (VGCF) with cutoff frequency calibration, a first-order all-pass filter, a programmable-gain amplifier, four independent dc-offset cancellation (DCOC) loops with on-chip capacitors, and a unit-gain ...
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Citations
... However, the filters in radar transceiver systems often suffer from severe DC offset problems that may cause saturation distortion of the entire system [9,10]. Several approaches have been proposed to address this issue, including AC coupling, analog high-pass filtering [11], DC negative feedback loops [12,13], and analog digital DC calibration [30,31,32]. However, these methods tend to occupy a large area of the System on Chip (SoC), and require extended response and stabilization time [14,15,16]. ...
This paper presents a lowpass filter for 5.8 GHz Doppler radar with an intermediate frequency signal hold function, which significantly reduces system power by interrupt mode operation. Additionally, it proposes a novel complementary push-pull DC offset calibration method to calibrate the DC voltage of the lowpass filter with the common mode voltage. Compared to traditional methods, the proposed scheme effectively stabilize the quiescent operating point of the receiver. The experimental results show that the power consumption of the proposed filter is 0.019 mW, calibrated DC voltage is 1.65 V, and residual DC voltage is less than 1 mV.
... The ACTBA [8] shown in Figure 3 follows the LNA through the capacitor C 2 with a value of 670 fF and converts the RF signals into differential signals, which are then down-converted to in-phase and quadrature low-IF differential signals by GMT. The crosscoupled structure composed of M 3 , M 4 , C 3 , and C 4 can reduce the noise from M 2 [14,22], and further reduce the Miller effect from the input transconductor stage of the ACTBA [8]. Ignoring the channel length modulation and body effects, the differential signal with equal amplitude and phase difference of 180 • can be obtained at output nodes outp and outn, as long as g m3 R 3 = g m4 R 4 holds. ...
A fully integrated low-power area-efficient receiver using a low–intermediate frequency topology for BDS-3 and GPS L1 bands is presented in this paper. Accurate localization can be achieved without requiring off-chip low-noise amplifiers. The receiver bandwidths for GPS and BDS-3 are 2 MHz and 4 MHz, respectively. Digitally assisted calibration schemes, such as RC calibration, automatic gain control, and DC offset correction are integrated to resist the effects of the process, voltage, and temperature (PVT) variations. The receiver—fabricated in a standard 55 nm CMOS technology—provides a maximum gain of 113.2 dB, a gain control range of 61 dB, and a minimum noise figure of 1.74 dB under a 1.2 V supply. The receiver, with and without the frequency synthesizer that provides the local oscillator frequency, consumes 8.7 mA and 4.8 mA, with areas of 0.73 mm2 and 0.345 mm2, respectively.
... Secondly, the DCR has a very serious DC offset problem which will not only reduce the IP2 of the receiver but can even saturate the subsequent circuit [1,12]. AC coupling [13] and a DC negative feedback loop [14][15][16] are popular methods to eliminate DC offset, but these methods often occupy a large amount of chip area and require a long DC stabilization time [17][18][19]. More and more receivers have eliminated DC offsets by digital methods, employing digital algorithms to control digital-to-analog converters (DACs) to compensate for DC offsets. ...
To improve the linearity of direct conversion receivers (DCRs), two high-linearity methods for high second-order intercept points (IP2s) and high third-order intercept points (IP3s) are proposed. To improve IP3s, a transconductance equalization technique for a complementary input operational amplifier (OPAMP) is proposed in an active-RC low-pass filter (LPF), while a digital-analog hybrid DC offset calibration (DCOC) method is proposed to improve IP2s. For one thing, the proposed transconductance equalization technique employs a pair of resistors to guarantee high voltage gain for an OPAMP with two-stage Miller topology under a high-input voltage swing to improve linearity with little deterioration of the noise performance. For another, during the DCOC method, the low-noise amplifier is turned off and replaced by an equivalent resistance of the output impedance of the low-noise amplifier to ensure the accuracy and effectiveness of the DCOC method. Fabricated in 40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of −53.2 dBm under the total voltage gain of 60 dB.
... With the trend of technology scaling down in advanced CMOS technology, the DC offset becomes the most serious problem, which will deteriorate the linearity performance and the SNR [4,5,6], especially for some high precision applications like biomedical imaging based on Doppler radar [6]. Although the DC offset can be removed by traditional analog methods like ac coupling [7] or LPF feedback loop [8,9,10,11], these methods take up a large area and have long pulse response time [9,12,13,14]. With the development of digital signal processing, many digital-assisted methods adopt DACs to compensate DC offset combined with digital logic. ...
This paper presents a DC offset calibration (DCOC) method combined with analog and digital circuits for direct conversion receivers. To work effectively, the LNA is shut off for better isolation and replaced by an equivalent resistance to keep the same transfer function of DC offset between calibration and operation. This method adopts DACs to compensate DC offset, then averages and eliminates the residual DC offset in the digital domain. Measurements show that this DCOC method achieves 0.44 mV DC offset and improves IM2 by 10dB. The DCOC circuits occupy 0.23 mm² in 40nm CMOS and consume 124uA at 1.3V supply.
... Where, ACWL is the accumulator word lengths in the DDSM as shown in Fig. 1. In our PLL design, LC VCO buffered output can be adjusted for the DVB-H/SH receiver application using a proper selection of the divider logic at the output of the LC VCO [16,17]. The LC VCO frequency is commonly generated two times of the desired specification of the hand-held mobile communication system for generating the exact I and Q signal. ...
A new and unique frequency divider circuit has been proposed for this work. In this paper, we have implemented a \(\varDelta \varSigma\) fractional-N PLL using a proposed pulse swallow based frequency divider and a programmable prescaler divider circuit. Advantages of the proposed pulse swallow based frequency divider circuit have been illustrated and its usefulness are described in details. This novel pulse swallow based frequency divider technique does not include any reset or reload signal for the swallow counter as it is normally triggered by the SR latch output signal in conventional pulse swallow based frequency divider circuit. Insertion of a variable delay element at the output of the program counter can be eliminated which is normally used to settle the problem of arrival of the falling edge of the swallow counter pulse. In addition, preset enable signal can be generated without any frequency dependent delay generation block and in few cases without selection of any frequency dependent RC network block. The residual phase noise output of the divider at 1 MHz offset frequency is \(-174.5\) dBc/Hz for a carrier signal frequency of 4.7 GHz and power consumption is 9 mW from a 1.2 V power supply. The design of the fractional-N PLL has been carried out in 130 nm standard CMOS process. There is no zero division in the proposed frequency divider’s swallow counter for any counting state due to the novel mathematical calculating algorithm for the pulse swallow divider circuit.
... Wideband applications, such as TV tuners [1,2] and softwaredefined radios [3,4], are commonplace where receivers have to deal with spurious mixing from a local oscillator (LO) harmonics. Tracking radio frequency (RF) filter [5][6][7][8] can be used to alleviate the interference because of the harmonic mixing. ...
... Unlike gate driven (GD) mixer biased with tail current source, where the drain current i D can be assumed as independent with LO when the transistors are on, here the LO will change i D of the transistors after turning them on, thus the analysis starts with the DC transfer function. The drain current of PMOS transistors based on the square-law model is (1) in which β p = (1/2)μ p C OX (W/L) p and the threshold voltage is ...
This paper presents the design and testing results of a complementary metal-oxide-semiconductor double-bulk harmonic-rejection (HR) mixer for wideband applications. An optimal gate-source bias voltage in the sub-threshold regime of the input transistor is found theoretically to achieve maxim HR by analysing the mixing mechanism of double-bulk mixer; and a double-bulk mixer has been designed and fabricated to verify the theoretical analysis. Test results substantiate the existence of the optimal bias point for HR of double-bulk-driven mixer when the sinusoidal local oscillator (LO) is applied. This simple but effective topology can achieve higher than 36, 44, 60 and 62 dB HR ratio for the third-, fifth-, seventh-and ninth-order of LOs, respectively, over broadband. The double-bulk mixer which input bandwidth is from 250 MHz to 3 GHz, including the buffer, consumes 5 mA current from 1 V power supply; the mixer core only consumes 1.5 mA current.
... The receiver satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T and can be utilized for a compact mobile digital TV tuner, which should be implemented with high performance, low power consumption, small size, and low cost for successful integration into mobile terminals. [7] JSSC 2009 [14] TCAS 2014 [15] This work Supporting standard DVB-H/T, T-DMB, ISDB-T DVB-H/T NA DVB-H/T, T-DMB, ISDB-T, ...
A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a 0.18-µm CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T-DMB, and ISDB-T with a digital demodulator. © 2015, Institute of Electronics Engineers of Korea. All rights reserved.
... The LNA specifications vary with different standards. For DVB-H, the NF should be less than 6.5 dB and the IIP3 larger than 0 dBm should be met [1,2]. Meanwhile, Bluetooth has a relatively relaxed demand with 5 dB NF and -4 dBm IIP3 [3]. ...
A 0.5-2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S-11 < -10 dB in the 0.5-2.5 GHz band. The noise figure (NF) is 3.9-5.0 dB and the IIP3 is 3.1-3.6 dBm. The power consumption is only 910 uW.
... However, even though the LNA has a gain of 23 dB, the following G m is saturated by the LNA output voltage swing. Thus, a minimum gain mode switch (M 5 and M 6 ) is added between the LNA and the G m [6]. As shown in In general, since active RC LPF shows higher linearity than G m C LPF, a 5th-order active RC Chebyshev LPF is adopted in this work [9 11]. ...
This paper presents a zero-IF CMOS RF receiver, which supports three channel bandwidths of 5/10/40MHz for LTE-Advanced systems. The receiver operates at IMT-band of 2,500 to 2,690MHz. The simulated noise figure of the overall receiver is 1.6 dB at 7MHz (7.5 dB at 7.5 kHz). The receiver is composed of two parts: an RF front-end and a baseband circuit. In the RF front-end, a RF input signal is amplified by a low noise amplifier and G_m with configurable gain steps (41/35/29/23 dB) with optimized noise and linearity performances for a wide dynamic range. The proposed baseband circuit provides a -1 dB cutoff frequency of up to 40MHz using a proposed wideband OP-amp, which has a phase margin of 77^{\circ} and an unit-gain bandwidth of 2.04 GHz. The proposed zero-IF CMOS RF receiver has been implemented in 0.13-?m CMOS technology and consumes 116 (for high gain mode)/106 (for low gain mode) mA from a 1.2 V supply voltage. The measurement of a fabricated chip for a 10-MHz 3G LTE input signal with 16-QAM shows more than 8.3 dB of minimum signal-to-noise ratio, while receiving the input channel power from -88 to -12 dBm.
... Currently existing DTV tuners only for UHF band have been implemented in BiCMOS [2], [3], but they are bulky and consume about 200 mW from a 2.8 V voltage supply. Deep submicron CMOS multiband tuners reported in [4] and [5] achieve low NF and high sensitivity, but they still consume more than 100 mW and occupy an area of 7 mm . All these tuners suffer from high power and large silicon area. ...
... To cope with this problem, the AC-coupling capacitor should be well selected to compensate the imaginary part in (2). And we can get (4) From (3) and (4), it is observed impedance matching can be realized by adding no matter how low is. Next, we will derive the voltage gain from to , abbreviated as , in condition of impedance matching. ...
This paper presents a direct-conversion DTV tuner for both VHF and UHF bands. The proposed tuner achieves a noise figure of 2.5-3.5 dB at VHF band and 2-3 dB at UHF band while the LNA consumes only 3.5 mW. An external band-pass LC filter is adopted for RF pre-filtering and providing DC conduction path for noise cancelling balun LNA. The system-level co-design of the LNA and pre-selecting filter further help to obtain 33 dB third-order harmonic rejection ratio without using harmonic rejection mixers. A quantization-noise-compensated fractional- N frequency synthesizer is implemented, achieving 0.5 ° integrated phase error (1 kHz to 4 MHz) at 666 MHz, and suppressing out-of-band ΣΔ noise by 20 dB. The proposed PLL injects compensation current into the loop filter during the PFD delay time, which precisely tracks the VCO output frequency. Highly reconfigurable analog baseband with 0.5-4 MHz bandwidth and 6-54 dB gain is integrated. The tuner is implemented in 65 nm CMOS process, occupies an area of 4.2 mm2, and consumes only 72 mW from a 1.2 V voltage supply.
