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Architecture efficiency comparison for Catapult C versus Xilinx IP core.

Architecture efficiency comparison for Catapult C versus Xilinx IP core.

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We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size (NF × NF) with O((NF)3) complexity to some FFT operations with O(NFlog2(F)) complexity and the inverse of some (N × N) submatrices. We then propose parallel and pipelined VLSI architectures wi...

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... in the parallel FFTs are studied extensively in multilevels, for example, the BFU level, the stage level, and the FFT-processor level. Catapult C scheduled RTLs for 32-point FFTs with 16 bits are com- pared with Xilinx v32FFT Core in Table 5 for a single FFT. Catapult C design demonstrates much smaller size for differ- ent solutions, for example, from solution 1 with 8 multipli- ers and 535 slices to solution 3 with only one multiplier and 551 slices. ...

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Citations

... The vector e k denotes a unit vector with a single " one " at cursor position k and " zeros " at all other positions. The calculation of the equalizer coefficients can efficiently be implemented using fast Fourier transform (FFT)-based algorithms, e.g., [42] and [43], or the conjugated gradient algorithm [44]. Such an equalizer therefore represents a low-complexity HSDPA receiver that is feasible for real-time implementation in a chip [45]. ...
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