Figure 1 - uploaded by Engin Afacan
Content may be subject to copyright.
Source publication
This study presents a parasitic-aware RF circuit
synthesis tool, in which layout-induced parasitics of passive
devices are captured by using sophisticated equivalent models
for them. Recently, analog circuit design has been fully automated,
where a circuit sizing is followed by a layout generator.
However, there is often a discrepancy between synth...
Context in source publication
Context 1
... is extremely sensitive to the layout design due to relatively larger layout-induced parasitics [3]. Therefore, layout-generation has also been automated to take into account the effect of layout-induced parasitics efficiently. Thus, the design loop has been com- pletely automated with the integration of sizing and layout tools as illustrated in Fig. 1. In [4], it has been shown that a few additional layout iterations can be sufficient to find a solution that still satisfies the performance con- straints after layout. However, the case for RF circuits is quite different since inclusion of layout-induced parasitics of passive devices (inductor and capacitor) causes severe performance ...
Similar publications
Current design of analog integrated circuits is still a time-consuming manual process resulting in static analog blocks which can hardly be reused. In order to address this problem, a new framework to ease reuse-centric bottom-up design of analog integrated circuits is introduced. Our IIP Framework (IIP: Intelligent Intellectual Property) enables t...
Citations
... The quality of the surrogate model and the available training data were the main challenge. Simulation-based RF design tool was introduced in [11], the optimization process was based on evolutionary algorithms. The simulated annealing technique was also employed. ...
... Optimization of a low noise amplifier and an operational amplifier were introduced in [2], where evolutionary algorithms were used. In [9], [10], [11], and [2] evolutionary algorithms may result in infinite optimization loops, they need good space exploration, and they do not offer assurance of convergence. Thus, evolutionary algorithms cannot be used in real type problems [12], [13]. ...
... Thus, evolutionary algorithms cannot be used in real type problems [12], [13]. In [11], simulatedannealing was used with evolutionary algorithms to get over the draw backs of the latter, yet the convergence is slow due to the incorporation of simulated-annealing. Simulationbased design automation of an LNA was introduced in [14]. ...
... Evolutionary algorithms were also used in the optimization of an operational amplifier (OPAMP) and an LNA, where the inductance modelling was carried out using linear behavior into performance models [17]. Evolutionary algorithms and simulated-annealing were used in the optimization of single ended LNA and CMOS differential cross coupled oscillator operating at 2.4 GHz frequency [18]. ...
... In addition, parasitic components are estimated such that the outcome of the design tool is close to the final design. The proposed design-aware tool does not require the design space exploration and/or the lengthy global optimization algorithms that were presented in the previous publications [11,[14][15][16][17][18]. The tool uses BFGS optimization algorithm, implemented within the virtuoso environment [19], as the core optimizer, and Spectre RF [20] as the simulation engine. ...
In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly linear RF power amplifiers. The main aim of the proposed tool is to speed up the design process of RF power amplifiers. In addition, it provides accurate final designs taking into consideration the effect of parasitic components of both active and passive devices. The proposed tool relies on the knowledge of designing highly linear RF power amplifiers. Both the optimization steps and design methodology are presented in this paper. The proposed tool is verified by designing a highly linear RF power amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node. The results show that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher than 24 dBm at 6 dB back-off power can be obtained.
... Design automation is mainly divided into two main categories, knowledge-based approach and optimization-based approach [1][2][3][4][5]. The main advantage of the former is the speed, while the disadvantage is the time needed to develop the knowledge database, done before the process. ...
... where B= 1 sL o1 +r o2 [ g m2 (sg m1 L int −1) /(s 2 g m1 c gs2 L int −sc gs2 +g m1 )+1]+ 1 sL op (5) where A v is the overall gain, s is Laplace variable s (= jω), gm 1 and gm 2 are the main and the cascode transistor's transconductance, respectively, (L o , L o1 , and L op ) are the inductors of the output matching network, L int is the interstage inductor between the main and the cascode transistors, c gs2 is the parasitic gate-to-source capacitance of the cascode transistor, and r o2 is the output resistance of the cascode amplifier. ...
... In addition, the RMS gain error between its different steps can be found using the: where N is the number of states, ∆S21 i is the step between the gain of state (i) and gain of state (i−1), and S21 step is the achieved gain step between the N states. Equation (5) indicates that the max gain depends on the output matching network parameters, the transistors transconductances, and the interstage inductor, and is inversely proportional to the source degenerated inductor. Furthermore, those parameters have a direct impact on the linearity (Input P1dB). ...
Designing millimeter-wave variable gain amplifiers (VGAs) is very challenging owing to the parasitic effects of the interconnects of both active and passive devices. An automated parasitic-aware optimization RF design tool is proposed in this paper to address this challenge. The proposed tool considers the parasitic effects prior to layout. It employs a knowledge-aware optimization technique. The augmentation between parasitic-aware and knowledge-aware techniques speeds up the design process and leads to a design as close to the final design after finalizing the layout. The proposed tool gives limitless and guaranteed converged solutions in a wide range of RF frequencies. A four-bits current steering VGA design is used as a validation of the tool. The tool is tested on three different frequencies using the 65 nm-technology node. The three tested frequencies (7, 10, and 13 GHz) show a root mean square gain error at approximately 0.1 dB and a phase variation at approximately 3.5° within a 16-dB gain control range. To our knowledge, it is the first reported automated design tool for a current steering VGA.
... In [29], an algorithm that performs RF circuits sizing by using evolutionary strategies and simulating annealing in the search and selection parts, respectively, is implemented in Matlab. The optimization is carried out taking into account the parasitics caused by the passive elements' layout through physical based equivalent parasitic models, by doing this the number of iterations between circuit sizing and layout generation is reduced (reducing the synthesis time) since the difference between synthesis and post-layout results is decreased. ...
The optimization of analog integrated circuits requires to take into account a number of considerations and trade-offs that are specific to each circuit, meaning that each case of design may be subject to different constraints to accomplish target specifications. This paper shows the single-objective optimization of a complementary metal-oxide-semiconductor (CMOS) four-stage voltage-controlled oscillator (VCO) to maximize the oscillation frequency. The stages are designed by using CMOS current-mode logic or differential pairs and are connected in a ring structure. The optimization is performed by applying differential evolution (DE) algorithm, in which the design variables are the control voltage and the transistors’ widths and lengths. The objective is maximizing the oscillation frequency under the constraints so that the CMOS VCO be robust to Monte Carlo simulations and to process-voltage-temperature (PVT) variations. The optimization results show that DE provides feasible solutions oscillating at 5 GHz with a wide control voltage range and robust to both Monte Carlo and PVT analyses.
... Commercial electronic design automation (EDA) circuit simulators like ADS, AWR, etc. have some restrictions in the case of highly complicated design problems with limited design time, and need processing large amount of data. Therefore, designing and sizing nonlinear RF/microwave circuits require an efficient computer-aided design (CAD) framework with optimization-based methodologies [1], [4]- [7]. New CAD tools have to be proposed to find design variables and optimal trade-offs between various objective functions efficiently and in the shortest time. ...
Power amplifier (PA) designs at high frequency are
not straightforward and they depend on designers’ experience
by dealing with a high number of parameters to be set. To
address PA design problems, we propose an automated bottomup method based on an artificial neural network (ANN) to be
employed in the optimization-oriented strategy. The proposed
methodology starts with a PA based on lumped elements (LEs),
then ANN is trained for characterizing the lumped element
PA and finally a PA with distributed components, the natural
environment at high frequency, is designed by using a bottomup method and the constructed ANN. In this way, the resulting
distributed element PA inherits the advantages of the lumped
element design, i.e. offering higher and flatter gain performance.
To validate our method, we design 10 W PAs in band frequency
of 1 GHz to 2 GHz (L band). The automated design of PA with
transmission lines (TLs) results in gain between 10-13 dB and
power added efficiency larger than 50%. Our results demonstrate
the robustness of the presented approach adopting ANN in
designing PAs, automatically.
... Over the past few years, several optimization-based methodologies for the automated sizing of analog and radiofrequency (RF) integrated circuits (ICs) have been proposed [1]- [9]. These methodologies link an optimization algorithm with a circuit performance evaluator (e.g., the Spectre RF simulator) to evaluate candidate solutions. ...
... For instance, most optimization-based design methodologies do not take into account sources of perturbation that affect the circuit performances such as process variability or layout parasitics. Although variability [5], [6] or layout parasitics [7]- [9] have been taken into account in some methodologies, they are always tackled separately during the optimization process. Another downside of previously reported synthesis methodologies pertains to the quality of the modeling used for passive components (e.g., inductors), which, in RF, are extremely important. ...
In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout-and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a multi-objective optimization algorithm to achieve a Pareto-optimal front containing optimal circuit designs offering different performance trade-offs. The final outcome of the proposed methodology is a set of design solutions (with their GDSII description available and ready-to-fabricate) that need no further designer intervention. Two key elements of the proposed methodology are the use of an optimization algorithm linked to an off-the-shelf simulator and an inductor model that yield EM-like accuracy but with much shorter evaluation times. Furthermore, the methodology guarantees the same high level of robustness against layout parasitics and variability that an expert designer would achieve with the verification tools at his/her disposal. The methodology is technology-independent and can be used for the design of radio frequency circuits. The results are validated with experimental measurements on a physical prototype.
... Over the past few years, several optimization-based methodologies for the automated sizing of analog and radiofrequency (RF) integrated circuits (ICs) have been proposed [1]- [9]. These methodologies link an optimization algorithm with a circuit performance evaluator (e.g., the Spectre RF simulator) to evaluate candidate solutions. ...
... For instance, most optimization-based design methodologies do not take into account sources of perturbation that affect the circuit performances such as process variability or layout parasitics. Although variability [5], [6] or layout parasitics [7]- [9] have been taken into account in some methodologies, they are always tackled separately during the optimization process. Another downside of previously reported synthesis methodologies pertains to the quality of the modeling used for passive components (e.g., inductors), which, in RF, are extremely important. ...
... Here, an IC extractor module was included to the evaluation part, where ICs of all transistors are determined and transmitted to the optimizer as well as the circuit specifications. During the evaluation of RF circuits, parasitic effects of passive devices are considered by using improved 2π models, where physical parameters of passive devices are also optimized as well as the electrical parameters [9]. The layouts and the corresponding equivalent models of the passive devices (meta- l-insulator-metal (MIM) capacitor and the planar inductor) are given in Fig. 4. ...
Thanks to the enhanced computational capacity of modern computers, even sophisticated analog/RF circuit sizing problems can be solved via electronic design automation (EDA) tools. Recently, several analog/RF circuit optimization algorithms have been successfully applied to automatize the analog/RF circuit design process. Conventionally, metaheuristic algorithms are widely used in optimization process. Among various nature-inspired algorithms, evolutionary algorithms (EAs) have been more preferred due to their superiorities (robustness, efficiency, accuracy etc.) over the other algorithms. Furthermore, EAs have been diversified and several distinguished analog/RF circuit optimization approaches for single-, multi-, and many- objective problems have been reported in the literature. However, there are conflicting claims on the performance of these algorithms and no objective performance comparison has been revealed yet. In the previous work, only a few case study circuits have been under test to demonstrate the superiority of the utilized algorithm, so a limited comparison has been made for only these specific circuits. The underlying reason is that the literature lacks a generic benchmark for analog/RF circuit sizing problem. To address these issues, we propose a comprehensive comparison of the most popular two evolutionary computation algorithms, namely Non-Sorting Genetic Algorithm-II (NSGA-II) and Multi-Objective Evolutionary Algorithm based Decomposition (MOEA/D), in this paper. For that purpose, we introduce two ad-hoc testbenches for analog (ANLG) and radio frequency (RF) circuits including the common building blocks. The comparison has been made at both multi- and many- objective domains and the performances of algorithms have been quantitatively revealed through the well-known Pareto-optimal front quality metrics.
This chapter presents and analyzes the state-of-the-art methodologies for analog and radio-frequency (RF) integrated circuit (IC) sizing automation. It starts by overviewing the main tools used to automate analog/RF circuit sizing in the past few decades, which can be divided into two major categories, i.e., knowledge-based and optimization-based. Afterward, related work using machine learning (ML) and deep learning (DL) techniques to enhance simulation-based optimizations will be presented and discussed, along with other works that tackle pure ML/DL-based sizing. Finally, a case study is introduced and some short conclusions taken, in order to set the starting point of the developments proposed in this book.KeywordsAnalog integrated circuit sizingElectronic design automationMachine learningSimulation-based synthesis
