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9: An example demonstration of cross-layer resource optimization during High Level scheduling using L2 Toffoli magic state preparation circuit. A block of Type-2 L1 Tiles used to perform seven L1 Toffoli gates can be reallocated to perform L2 error correction
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A study which explores optimized novel designs for large scale quantum computer based on realistic noisy hardware
Citations
... Furthermore, the physical implementations of quantum operations in any technology are imperfect [4] [5]. Quantum noise, due to decoherency of quantum states and imperfect quantum operations, is the most important challenge in constructing large-scale quantum computers [3][6] [7]. ...
... The method proposed by Paetznick and Reichardt [13] is a known example of this approach. This method has been described based on the [ [15,7,3]] quantum Hamming code as an example. In this code, by considering the first logical qubit as data qubit and fixing the other six logical qubits into the encoded |0 ⊗6 state as gauge qubits, CCZ gate will be transversal. ...
As there is no quantum error correction code with universal set of transversal gates, several approaches have been proposed which, in combination of transversal gates, make universal fault-tolerant quantum computation possible. Magic state distillation, code switching, code concatenation and pieceable fault-tolerance are well-known examples of such approaches. However, the overhead of these approaches is one of the main bottlenecks for large-scale quantum computation. In this paper, two approaches for universal fault-tolerant quantum computation, mainly based on code concatenation, are proposed. The proposed approaches outperform code concatenation in terms of both number of qubits and code distance and has also significantly less resource overhead than code switching, magic state distillation and pieceable fault-tolerance at the cost of reducing the effective distance of the concatenated code for implementing non-transversal gates.
... Several papers [26][27][28][29][30][31] have discussed how to map FT quantum circuits onto 2D quantum architectures based on concatenated codes such as Steane code. However, not many papers focus on surface code (SC) [32], currently one of the most promising QEC codes. ...
... Note that two CNOT gates which share the same control or the same target qubit are commutable, meaning that they can be executed in any order except in parallel. This commutation property has not been considered in previous works [11][12][13][14][15][26][27][28][29][30][31]. In this paper, we take commuted CNOT gates into account and replace the optimization condition (2) with conditions (3) and (4): ...
Quantum error correction (QEC) and fault-tolerant (FT) mechanisms are essential for reliable quantum computing. However, QEC considerably increases the computation size up to four orders of magnitude. Moreover, FT implementation has specific requirements on qubit layouts, causing both resource and time overhead. Reducing spatial-temporal costs becomes critical since it is beneficial to decrease the failure rate of quantum computation. To this purpose, scalable qubit plane architectures and efficient mapping passes including placement and routing of qubits as well as scheduling of operations are needed. This paper proposes a full mapping process to execute lattice surgery-based quantum circuits on two surface code architectures, namely a checkerboard and a tile-based one. We show that the checkerboard architecture is 2x qubit-efficient but the tile-based one requires lower communication overhead in terms of both operation overhead (up to ~86%) and latency overhead (up to ~79%).
... Several papers [26][27][28][29][30][31] have discussed how to map FT quantum circuits onto 2D quantum architectures based on concatenated codes such as Steane code. However, not many papers focus on surface code (SC) [32], currently one of the most promising QEC codes. ...
... Note that two CNOT gates which share the same control or the same target qubit are commutable, meaning that they can be executed in any order except in parallel. This commutation property has not been considered in previous works [11][12][13][14][15][26][27][28][29][30][31]. In this paper, we take commuted CNOT gates into account and replace the optimization condition 2 with conditions 3 and 4: ...
Quantum error correction (QEC) and fault-tolerant (FT) mechanisms are essential for reliable quantum computing. However, QEC considerably increases the computation size up to four orders of magnitude. Moreover, FT implementation has specific requirements on qubit layouts, causing both resource and time overhead. Reducing spatial-temporal costs becomes critical since it is beneficial to decrease the failure rate of quantum computation. To this purpose, scalable qubit plane architectures and efficient mapping passes including placement and routing of qubits as well as scheduling of operations are needed. This paper proposes a full mapping process to execute lattice surgery-based quantum circuits on two surface code architectures, namely a checkerboard and a tile-based one. We show that the checkerboard architecture is 2x qubit-efficient but the tile-based one requires lower communication overhead in terms of both operation overhead (up to 86%) and latency overhead (up to 79%).
... Furthermore, quantum computation must be implemented on a piece of hardware with the quantum mechanical properties while the physical implementations of quantum operations in any technology are imperfect [4] [5]. Quantum noise due to decoherency of quantum states and imperfect quantum gates ranks on the top of the challenges in constructing large-scale quantum computers [3][6] [7]. ...
... The method proposed by Paetznick and Reichardt [17] is a known example of this approach. This method is described based on the [ [15,7,3]] quantum Hamming code as an example. In this code, by considering the first logical qubit as data qubit and fixing the other six logical qubits into encoded |0 ⊗6 state as gauge qubits, CCZ gate will be transversal. ...
As there is no quantum error correction code with universal set of transversal gates, several approaches have been proposed which in combination of transversal gates make universal fault-tolerant quantum computation possible. Magic state distillation, code switching, code concatenation etc. are well-known examples of such approaches. However, the overhead of these approaches is one of the main bottlenecks for large-scale quantum computation. In this paper, a hybrid approach is proposed which combines the code concatenation with the code switching or magic state distillation schemes. The proposed approach is superior to code concatenation in terms of both resource overhead and error threshold and also significantly reduces the resource overhead of code switching and magic state distillation at the cost of sacrificing the full distance of the concatenated code for the implementation of non-transversal gates.
Computer performance improvement is one of the biggest challenges. The technology has moved towards increasing the performance by using Quantum computing which improves 20 times to decrypt the code compared to the classical computer. Quantum computing is computing which uses quantum mechanical phenomena. The main purpose of the quantum computing is to find algorithms which are considerably faster than the classical algorithms for solving the same problem. In this paper we are proposing the tools of quantum computing and different quantum algorithms. These ideas are first applied to classical computer and then to the quantum computer. We are also focusing on the architecture of quantum computing which is existing in literature.
A number of quantum processors consisting of a few tens of noisy qubits already exist, and are called Noisy Intermediate-Scale Quantum (NISQ) devices. Their low number of qubits precludes the use of quantum error correction procedures, and then only small-size quantum algorithms can be successfully run. These quantum algorithms need to be compiled to respect the constraints imposed by the quantum processor, known as the mapping or routing problem. The mapping will result in an increase of the number of gates and circuit depth, decreasing the algorithm's success rate. In this paper, we present a mapper called Qmap that makes quantum circuits executable on the Surface-17 processor, a scalable processor with a surface code architecture. It takes into account not only the elementary gate set and qubit connectivity constraints but also the restrictions imposed by the use of shared classical control, which have not been considered so far. Qmap is embedded in the OpenQL compiler and uses a configuration file where the processor's characteristics are described and that makes it capable of targeting different quantum processors. To show this flexibility and evaluate its performance, we map 56 quantum benchmarks on two different superconducting quantum processors, the Surface-17 (17 qubits) and the IBM Q Tokyo (20 qubits), while using different routing strategies. We show that the best router can reduce the resulting overhead up to 80% (72%) for the number of gates and up to 71.4% (66.7%) for the circuit latency (depth) on the Surface-17 (IBM Q Tokyo) when compared to the baseline (trivial router). In addition, having a slightly higher qubit connectivity helps to decrease the number of inserted movement operations (up to 82.3%). Finally, we analyze how the mapping affects the reliability of some small quantum circuits. Their fidelity shows a decrease that ranges from 1.8% to 13.8%.
