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We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usually are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip...
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... be partitioned into two double-MSA (DMSA) modules, DMSA1 and DMSA2, in the test mode, where DMSA1 and DMSA2 rep- resent, respectively, the upper and lower MSA pairs in Fig. 6. An -point FFT network thus can be viewed as formed by the separate DMSA1 and DMSA2 networks. For example, the eight-point FFT butterfly network in test mode is as shown in Fig. 7. In test mode, the functions of DMSA1 are (6) and the functions of DMSA2 are (7) From (6) and (7), we see that DMSA1 and DMSA2 have bi- jective functions if and , i.e., and . The M-testability condition for an -point FFT butterfly network based on the DMSA1 (DMSA2) is described in thm 1 (see Appendix I-A for its proof). In what ...
Citations
... Feature extraction is very important because the in-depth and hidden features of singlefault patterns can be detected through frequency subband decomposition. Referring to the existing literature, many classical feature extraction techniques were applied to fault diagnosis; the most typical one is the fast Fourier transform (FFT) [10][11][12][13]. However, its main drawback is the unsuitability for nonstationary patterns. ...
Engine ignition patterns can be analyzed to identify the engine fault according to both the specific prior domain knowledge and the shape features of the patterns. One of the challenges in ignition system diagnosis is that more than one fault may appear at a time. This kind of problem refers to simultaneous-fault diagnosis. Another challenge is the acquisition of a large amount of costly simultaneous-fault ignition patterns for constructing the diagnostic system because the number of the training patterns depends on the combination of different single faults. The above problems could be resolved by the proposed framework combining feature extraction, probabilistic classification, and decision threshold optimization. With the proposed framework, the features of the single faults in a simultaneous-fault pattern are extracted and then detected using a new probabilistic classifier, namely, pairwise coupling relevance vector machine, which is trained with single-fault patterns only. Therefore, the training dataset of simultaneous-fault patterns is not necessary. Experimental results show that the proposed framework performs well for both single-fault and simultaneous-fault diagnoses and is superior to the existing approach.
This paper deals with diagnosis and design for diagnosability at the system level. In particular, diagnosis and design for diagnosability of high-end Internet routers in manufacturing test and design validation are considered. A packet flow model is used for diagnosis down to the replaceable unit level. The diagnosis method operates correctly when there are multiple or intermittent faults. A diagnosability criterion is proposed and a method for assessing diagnosability of various designs given. The paper concludes with a description of empirical results from an industrial application of the diagnosis method
This paper presents efficient testing methodologies for conditional sum adders. A conditional sum adder consists of conditional cells and selection cells. We propose a design-for-testability (DFT) technique to modify the conditional cells of a conditional sum adder. Then a test scheme is used for detecting the conditional sum adder with single cell fault model (CFM). The proposed test scheme only needs very low-test complexity to test a conditional sum adder. For example, the number of test patterns for a 64-bit conditional sum adder is only 9. The ratio of the number of test patterns of the proposed test scheme to the number of the test patterns of the previous scheme (Becker et al., 1995) is only about 1%. Also, experimental results show that the area overhead is only about 2.8% for a 64-bit conditional sum adder with the DFT scheme.
