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This paper gives an overview of some of the effects caused by
circuit mismatch and parasitics in binary weighted digital-to-analog
converters (DACs), and, as a special case, a current-steering CMOS
converter. Matlab is used as a behavior-level simulator. In
telecommunications applications, the frequency-domain parameters are of
the greatest importa...
Contexts in source publication
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... use of switched current sources is a straightforward approach in high-speed CMOS DAC's, since currents are easy to weight, sum, and switch. The structure that is studied in this paper is a binary weighted converter as shown in Fig. 1 and discussed in [6]- ...
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... switches, , in Fig. 1, are controlled by the digital bits, , where is the number of bits. The digital input number is , , , , with as the most significant bit (MSB) and the least significant bit (LSB). When is high, switch is closed and the current is switched to the output. Binary weighting implies that the current source controlled by , i.e., the th LSB ...
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... the input, it will give rise to a signal-dependent gain, i.e., distortion. Using (5) and assuming a signal-dependent output conductance of the DAC , the current delivered to the load is (6) where indicates the DAC's digital input given by (3) and is the load resistance. The output conductance is determined by studying the DAC structure shown in Fig. 1, and is related to the number of parallel-unit current sources that are currently switched to the output (determined by the digital input). The output conductance associated with one- unit current source is assumed to be and with the th LSB, we have the corresponding conductance . The total output conductance of the converter is given ...
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... Fig. 10, we show the average simulated and calculated SFDR for a 10-, 12-, and 14-bit DAC. The value is found by taking the average from 1024 simulations for each mismatch value. In Fig. 11, we show the typical output spectrum of a 14-bit DAC when applying matching errors with standard deviation %. The SFDR is approximately 83 dBc for a ...
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... Fig. 10, we show the average simulated and calculated SFDR for a 10-, 12-, and 14-bit DAC. The value is found by taking the average from 1024 simulations for each mismatch value. In Fig. 11, we show the typical output spectrum of a 14-bit DAC when applying matching errors with standard deviation %. The SFDR is approximately 83 dBc for a full-scale sinusoid ...
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... matching errors of the unit sources are correlated if they are densely placed close to each other [5], [14]. The mismatch error for the th unit source associated with the th bit is denoted . The expectation value of the squared output current for bit is (59) Fig. 10. Calculated and simulated SFDR versus mismatch for a 10-, 12-, and 14-bit DAC. Fig. 11. Output spectrum for a 14-bit DAC with mismatch size approxi- mately ...
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... general, the output impedance of the current-steering DAC is varying with the signal. With each unit current source, a certain output resistance is associated. In the same way, we include a capacitance, . Hence, for the th current source, we will have a capacitance , and similar to (7), at the code we have a total output capacitance of . In Fig. 12, we show this situation, where we have included a parasitic capacitance and resistance and . As illustrated in Fig. 13, a code transition at the input will give rise to a glitch and a step function at the output, where the glitch energy and the rise time are dependent on the codes. The first-order model gives the output current through ...
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... a certain output resistance is associated. In the same way, we include a capacitance, . Hence, for the th current source, we will have a capacitance , and similar to (7), at the code we have a total output capacitance of . In Fig. 12, we show this situation, where we have included a parasitic capacitance and resistance and . As illustrated in Fig. 13, a code transition at the input will give rise to a glitch and a step function at the output, where the glitch energy and the rise time are dependent on the codes. The first-order model gives the output current through the load [6] to (65) where . is the current through the load at the beginning of the code- transition, is the end ...
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... and bit skew, i.e., all bits do not switch exactly at the sampling point, and hence it is important to have a proper digital delay for all bits [4], [17], [18]. For example, if the MSB switches faster than all other bits at the code transition 011 11 100 00, we may for a short period of time have the code 111 11 at the output, giving a glitch (Fig. 13). The common way to guarantee a good design is to guarantee that the glitch energy is kept as low as possible [2], by for example using segmentation and proper switching schemes ...
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... slewing is dependent on the change of the input code, but the glitches are more dependent on the bits changing. A large glitch will also result in a longer settling time. In Fig. 14, we show how this skew can be characterized for the th bit. The errors of switching time are given by the timing errors . The switching activity of bit is determined by Hence, for the th bit, we will have a pulse-shaped error current (as shaded in Fig. 14). Using (72), the total skew error current is (74) For a full segmentation of the ...
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... on the bits changing. A large glitch will also result in a longer settling time. In Fig. 14, we show how this skew can be characterized for the th bit. The errors of switching time are given by the timing errors . The switching activity of bit is determined by Hence, for the th bit, we will have a pulse-shaped error current (as shaded in Fig. 14). Using (72), the total skew error current is (74) For a full segmentation of the data, the switching activity would be determined by the signal change or derivative. Now the situation is more complex, since the bits are determining the size of the glitches. The time skew may be in the same order for all bits, but the MSB's will ...
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... Fig. 15, we show the output spectrum of a single-ended output of the converter. The sample frequency is 25 MHz and the signal frequency 670 kHz. The input signal amplitude is 15 dBFS . The distortion with respect to the second harmonic HD is approximately 59 dBc, and for the third harmonic HD we have 57 dBc. In measurements, we have also found ...
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... a function of the signal amplitude, the measured dis- tortion with respect to the second and third harmonic is also shown in Fig. 16. When varying the ac value of the signal and keeping the dc value constant, it is seen that HD is approximately constant and HD is decreasing by 6 dB for each doubling of the signal's amplitude. This follows the result found in (20). We see from the equation that if the dc value is small compared to the value, the SFDR should be ...
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... Fig. 17 we show the simulated output spectrum of a single-ended 14-bit converter, where the output impedance of each unit current source is 2.9 G , the load resistance is 25 , parasitic resistance is approximately 375 , the capacitance associated with each current source is approximately 4 fF, and the parasitic capacitance 40 pF. The sampling ...
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... current source is 2.9 G , the load resistance is 25 , parasitic resistance is approximately 375 , the capacitance associated with each current source is approximately 4 fF, and the parasitic capacitance 40 pF. The sampling frequency is 25 MHz and the signal frequency is 670 kHz, and the ac signal is 15 dBFS. Compare with the measured spectrum in Fig. 15. The performance of the converter may be predicted using Matlab ...
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Citations
... The model in [35] approximates glitch behaviour by opposite ramp-signals that are offset in time, and similar models are presented in [38] using piece-wise linear approximations. In [4,36] glitches are modelled as rectangular pulses, and in [37] a function comprised of hyperbolic and trigonometric expressions is used to approximate the glitch shape. The model in [33] superimposes two arbitrary functions to obtain a good glitch approximation, which also allows Fourier-analysis of the distortion. ...
... The construction of ∆y i (t) is illustrated in Fig. 1. If g i = 1 this model is equivalent to the models in [4,36], and since the functions n i can be chosen arbitrarily, with appropriate choices, the model can be made identical to the models presented in [33,35,37]. Note that in Sec. ...
... between the Laplace transformed A(s) and G N (s) of α(t) and N (x(t)), respectively, with s = σ + iω. The error bound (36) can further be elaborated on to obtain a conclusion in analogue with (30). For this, let r(u) ≜ H(u + ρ) − H(u) denote a rectangle function expressing the interval J t of width ρ, with H(u) the Heaviside step function (1). ...
Glitches introduce impulse-like disturbances which are not be readily attenuated by low-pass filtering. This article presents a model that describes the behaviour of glitches, and a method for mitigation based on a large-amplitude dither signal. Analytical and experimental results demonstrate that a dither signal with sufficient amplitude can mitigate the effect of glitches, when used in conjunction with a low-pass filter. The dither signal in conjunction with low-pass filtering essentially converts a glitch from a high-frequency to low-frequency disturbance.
... The model in [35] approximates glitch behaviour by opposite ramp-signals that are offset in time, and similar models are presented in [38] using piece-wise linear approximations. In [4,36] glitches are modelled as rectangular pulses, and in [37] a function comprised of hyperbolic and trigonometric expressions is used to approximate the glitch shape. The model in [33] superimposes two arbitrary functions to obtain a good glitch approximation, which also allows Fourier-analysis of the distortion. ...
... The construction of ∆y i (t) is illustrated in Fig. 1. If g i = 1 this model is equivalent to the models in [4,36], and since the functions n i can be chosen arbitrarily, with appropriate choices, the model can be made identical to the models presented in [33,35,37]. Note that in Sec. ...
... between the Laplace transformed A(s) and G N (s) of α(t) and N (x(t)), respectively, with s = σ + iω. The error bound (36) can further be elaborated on to obtain a conclusion in analogue with (30). For this, let r(u) H(u + ρ) − H(u) denote a rectangle function expressing the interval J t of width ρ, with H(u) the Heaviside step function (1). ...
This paper develops and experimentally evaluates a dither-based method for improved generation of arbitrary signals in digital-to-analogue converters that exhibits glitches --- essentially converting the glitches from high-frequency to low-frequency disturbances. One major benefit of this behaviour appears in closed-loop control applications, as the glitch disturbance can be moved from outside control law bandwidth to inside control law bandwidth, enabling suppression by feedback. A behavioural model of glitches is presented and the effect of applying a dither signal is analysed in detail. Analytical and experimental results demonstrate that a dither signal with sufficiently large amplitude can mitigate the effect of glitches, when used in conjunction with a low-pass filter. Severe glitches appear in various digital-to-analogue converter topologies, including converter topologies that are used in high-precision motion control applications, such as adaptive optics and scanning force microscopy. Glitches introduce impulse-like disturbances which have a broadband frequency distribution. Low-pass filtering alone does not provide sufficient attenuation, and in applications with feedback control only frequency content within the control law bandwidth is attenuated. Hence, a high-frequency disturbance such as a glitch will not be suppressed. The use of dithering to suppress glitches is therefore beneficial in applications where errors in signal conversion are a primary concern, such as high-precision motion control or accurate reference signal generation.
... This particular approach requires complicated mathematical simulation models of the DAC in order to define the influence of each code on its actual output voltage [10]. Also, DAC was modeled to show the effect of parasitic element and component mismatching on the converter performance [11]. However, other noise sources such as power supply and other hardware inputs were not included [7]. ...
... In this study, the DWT algorithm was applied to decompose ( ) x t using multi-resolution techniques and a combination of low-and high-frequency components. While lowfrequency components are stationary over a period of time (approximation coefficients), high-frequency components are noisy and provide detail coefficients as shown in equations (11) and (12), respectively [21]. ...
In selecting Digital-to-Analog converters, overall performance
accuracy is a primary concern; that is, how close does
the output signal reflect the input codes. Integral NonLinearity
(INL) error is a critical parameter specified by manufacturers
to help users determine device performance and application
accuracy. In classical testing of INL error, for an nbit
DAC, 2n output levels must be included in the computation.
This leads to a time-intensive and costly process.
Therefore, the authors investigated the ability of Wavelet
Transform to estimate INL with fewer samples in real-time
testing. Compared with classical testing, the novel implementation
of this Wavelet Transform has shortened testing
times and reduced computational complexity based on special
properties of the multi-resolution process. As such, the
Discrete Wavelet Transform can be especially suitable for
developing a low-cost, fast-test procedure for highresolution
DACs.
... The static behavior is determined by the settled output values while the dynamic properties are determined by the transition between two states. The later includes slewing, glitches, time skew, etc. [20]. Since in CM-SAR, precision is only required during the comparator decisions, the dynamic errors requirements of the presented system are not as stringent as those for the overall DAC resolution, as it is usually the case for CM-DACs where the entire settling process must be taken into account. ...
... , since 2 i unit current sources are connected in parallel [20]. In our design, we aim for a 3r yield, meaning that 99.7 % of the converters must have an integral nonlinearity (INL) smaller than 0.5 least significant bit (LSB) [6]. ...
... The largest current transition, which in our system occurs when switching the most significant bit (MSB), suffers the largest error DI. This error can be expressed as [20]: ...
A 10-bit 50 MS/s current-mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. Due to the absence of a switched capacitor feedback DAC, the value of the sampling capacitance can be chosen solely based on the kT/C noise required to achieve a certain performance. Then by designing the input Gm stage for a wide differential input voltage range, the resulting sampling capacitance value can be made significantly smaller compared to a conventional switched capacitor SAR ADC. Moreover, the presented design requires neither an external reference voltage to bias the Gm stage output nor a low-impedance DAC-reference voltage. To validate the proposed approach, a prototype 10-bit ADC is fabricated in a 90 nm TSMC CMOS process. Measured results of the ADC show an SFDR of 58.4 dB at 50 MS/s, while consuming 6 mW from a 1.2 /1.8 V supply.
... The M2M-ladder-type current-steering DAC is adopted for reducing area and power dissipation, and it consumes 85 μW at 10 MHz with 6-bit resolution. The conventional currentsteering DACs are a unit element-generic type [13] and a binary weighted type [14]. Both types increase steering current and current-steering device sizes exponentially when the bit number increases. ...
A design of a new hybrid-type digital pulsewidth modulator (DPWM) with a wide frequency range of 1000 : 1, from 10 kHz to 10 MHz, is presented. The proposed DPWM has the maximum duty-cycle resolution of 11 bits and consumes the power of 17.5 μW at 10 kHz and 2.36 mW at 10 MHz, respectively. The proposed DPWM realizes the upper 5-bit resolution using a programmable digital counter and the lower 6-bit resolution using a current-integrating-type phase interpolator, employing an M2M-ladder current-steering digital-to-analog converter for low power consumption. The operating clock is generated in on-chip using a relaxation oscillator. The prototype integrated circuit fabricated in a 0.25-μm high-voltage complementary metal-oxide-semiconductor demonstrates that the proposed DPWM maintains a good linearity across the entire operating range.
... Commercial developments have been primarily in circuit designs that take advantage of advances in semiconductor processes. Improved mathematical modelling of ADCs to better predict SFDR generation is also a concern [14], [15]. The specification of mobile handsets and base stations drives commercial designs. ...
The dynamic range of an analogue to digital converter (ADC) can be specified in several ways which are application dependent. This problem has been addressed in industry by the International Electro-technical Commission (IEC) standard for dynamic specifications for ADCs [1]. The most often used specification for RF applications is Spurious Free Dynamic Range (SFDR). This is specified in the frequency domain through analysis of a suitable test signal such as two tones of equal amplitude. SFDR then indicates the range in amplitude between the maximum test signal amplitude and the amplitude of any unwanted or spurious signal. These spurious signals may be related to the presence of the test signal or they may be from other sources.
... These effects are usually described by their influence on the integral nonlinearity (INL). The static matching of the current sources sets an upper limit to the achievable INL and therefore also to the distortion performance of the D/A converter [4]. The matching error between the current cells consists of a random and a systematic component that both have to be tackled. ...
... equals the number of unit cells, and is the load impedance. For the model presented in Fig. 1 and assuming that is sufficiently big the output impedance of the cell can be approximated by (4) In this equation signifies the voltage gain of the current switch transistor. If this transistor operates in saturation its voltage gain is . ...
... Based upon the analysis presented in Section II, a design plan for maximum dynamic linearity can be derived. First it should be ensured that the static mismatch of the current sources does not impose an upper bound on the achievable linearity [4]. Equation (1) indicates that the area of the current source array (CSA) can be traded off with transistor overdrive voltage for a given mismatch specification. ...
This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design strategy is proposed that introduces a switch-driver power consumption aware analysis of the switched current cell. The analysis of the major distortion mechanisms in the switched current cell allows the derivation of a design strategy for maximum linearity. This strategy is extended to include the power consumption of the switch drivers in function of the switched current cell design. To minimize the digital power consumption, low-power implementations of the thermometer decoder and switch driver circuits are introduced.
... Segmented architectures are widely used in high-speed and high-accuracy digital-to-analog converters (DAC's) [1], [4]– [10].Fig.1 shows a segmented current steering DAC (CS DAC) in which the least significant bits (LSB's) are realized using a binary-weighted array and the most significant bits (MSB's) are thermometer decoded (and implemented with a unary array). Increasing the number of thermometry bits guarantees the monotonocity, reduces the glitch energy (caused by timing mismatch error of the switches while the input code is changing), reduces the Total Harmonic Distortion and increases the linearity of the converter [1]. ...
... Since σ rel is inversely proportional to the square root of the current source transistor area [3], a considerable reduction in the current source transistor area will be possible. On the other hand, according to (1), by increasing the unary-weighted random mismatch, the value of SFDR decreases [10].Figure 7 shows the SFDR characteristic versus σ rel in the mentioned converter according to (1) and the simulation results in the conventional structure and the proposed structure with four possible connections between sub-arrays and the control levels. According to this figure, by changing the unary-weighted random mismatch distribution, the spurious harmonic amplitude also changes and the probability of reaching to a higher SFDR increases.Figure 5. INL distribution in 1000 simulations for (a) conventional row-column, and the proposed decoding architecture with index interface of (b) 4, (c) 8 and (d) 12 between sub-arrays and control levels.Figure 6. INL-Yield vs. standardd deviation: (a) conventional, the poposed decoding architecture with (b) 4 (c) 12 and (d) 23 index interface.Figure 7. SFDR vs. sigma(I)/I in formula, conventional and the proposed architecture with 4 pattern interface between sub-arrays and control levels. ...
... Segmented architectures are widely used in high-speed and high-accuracy digital-to-analog converters (DAC's) [1], [4] [10]. Fig.1 shows a segmented current steering DAC (CS DAC) in which the least significant bits (LSB's) are realized using a binary-weighted array and the most significant bits (MSB's) are thermometer decoded (and implemented with a unary array). ...
In this paper, a novel architecture for implementation of segmented Digital-to-Analog Converters (DACs) has been proposed. In this architecture, the array of unit elements has been divided into four similar sub-arrays and binary to thermometry conversion is performed in three control levels. The proposed control levels are connected to the sub-arrays in different sequences, thus different analog outputs according to the random mismatch distribution of sub-arrays is achieved. This architecture in addition to an extra multiplexer provides the possibility to test the chip after its fabrication in different sequences and the most linear one based on static linearity metric (INL-Yield) or dynamic performance (SFDR) be selected. Monte-Carlo simulations for an 8-bit unary DAC has shown that in the proposed architecture the probability of achieving a more linear DAC is much more than conventional one. Hence, preserving the required linear output, the mismatch of the unary elements could be increased i.e. the area of the unary array and the whole chip could be decreased.
... To ensure clock synchronization, a specific clock distribution scheme, such as an H-tree or a grid topology, need to be employed. SFDR is also affected by the output impedance of the DAC [16]. For an N-bit DAC with a switching structure as shown in Fig. 9, the SFDR can be estimated as (6) where is the output impedance at the drain, or collector, of each switch, and is the load resistance for the DAC output. ...
This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse sine-weighted DAC and eight 3-bit fine sine-weighted DACs, the core area of the DDS is 3 �? 2.5 mm2. The maximum clock frequency was measured at 8.6 GHz with a 4.2958 GHz output. The DDS consumes 4.8 W of power using a single 3.3 V power supply. It achieves the best reported phase and amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 GHz·2SFDR/6/W in the mm-wave DDS design. The measured spurious-free-dynamic-range (SFDR) is approximately 45 dBc with a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHz output in the Nyquist band at the maximum clock frequency of 8.6 GHz. Under a 7.2 GHz clock input, the worst-case Nyquist band SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is - 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.
... This particular approach requires complicated mathematical simulated models of DAC to define the influence of each code on its actual output voltage [11]. Also, In [12], DAC was modeled to show the effect of parasitic element and component mismatching on the converter performance. However, other noise sources such as power supply and other hardware inputs were not included [7]. ...
In selecting Digital-to-Analog converters, overall accuracy performance is a primary concern; that is, how close does the output signal reflect the input codes. Therefore, Effective Number of Bits (ENOB) is a critical parameter specified by manufactures (directly and indirectly) to help users determining device performance and applications accuracy. In classical testing via FFT SNR, noise summation influence can misrepresent the estimation of the device active number of bits. In addition, this estimation can be complicated and lengthy. Therefore, in this work, we investigate the ability of wavelet transform to estimate ENOB with less samples in real time testing. Compared with FFT testing, our novel implementation of the wavelet transform has shortened testing times and reduced computation complexity based on the special properties of the multi-resolution process. As a result, Discrete Wavelet Transform can be especially suitable for developing a low-cost, fast testing procedure even for high resolution DACs.
