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With the advent of adiabatic logic, the MOS-based digital circuit design has shown improvement by leaps and bounds in terms of reducing power. In the same quest, an adiabatic logic family called the Adiabatic Array Logic is used to design some fundamental logic gates- NOT, NAND, NOR and XOR, which shows significant improvement in power dissipation...
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... , !X:< For a given input, the adiabatic gate is operating as parallel transmission gate chains, which for each time slot have at least one path between the sinusoidal power clock, and the output node set to a logic one. This circuit can be analysed in the same way as done for fig. 2, where, the equivalent resistance R is given by ...
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Citations
... Both logic families use feedback mechanism which tends to slow down the operating frequency of circuit. A number of adiabatic circuits proposed in literature operate in the frequency range of 100 − 500 MHz [37][38][39][40]. Such low frequency requires massive parallelism of processing components to achieve the target throughput. ...
... The performance results of both CN implementations are summarised in Table 12. The table first demonstrates that the proposed design achieves a high frequency as compared to the designs of [37][38][39] based on adiabetic switching. This is because an effort is devoted to keep the ring size as small as possible to obtain the desired Boolean function implementation. ...
Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information‐lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low‐power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90nm complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post‐layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post‐layout area of 0.013 mm², achieves up to 4.3 GHz frequency and consumes 52μW power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.
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This paper presents the derivation of the most energy-efficient source functions by using calculus of variations. The fundamental theorem of calculus of variations for finding the functions that are local minima or local maxima of the integral is first explained. The theorem is then applied to derive analytically the source functions that minimize energy dissipation in circuits during transient. In particular, the most energy-efficient input current function and voltage source function for charging series R-C circuit are derived and proved to be a constant function and a raised ramp function respectively. The theorem of calculus of variations is extended for other common first order linear circuits as well. Their most energy-efficient source functions and lowest energy dissipation expressions are summarized in compact parameters involving speed and energy trade off limits. Numerical results are illustrated to depict the upper limit of speed-energy trade off and to justify the consistency with the analytical results. Application of the most energy-efficient source function for charging and discharging the capacitor of supercapacitor and adiabatic circuits is discussed along with comparison with other functions.
For modern portable devices, power consumption is an important factor. Adiabatic is an efficient logic style that can be implemented for low power digital system. In this work, full adder has been adopted as the adiabatic logic circuit in sub-threshold regime. In this article performance analysis of conventional as well as adiabatic adder has been performed for the performance analysis, 1-Bit, 4-Bit, 8-Bit and 16-Bit adders have been considered. The power dissipation has been represented as power gain which is given by the ratio of power dissipation in conventional adder to power dissi-pation in adiabatic adder. Also, impact of High-K dielectric materials on the performance of adiabatic logic circuit has been performed in depth. Energy Efficient Sub-Threshold Adiabatic Logic (EESAL) has been adopted as the reference circuit. Moreover, analytical modelling has been performed for the used adiabatic logic circuit. Supply voltage, frequency, load and temperature have been taken as the varied parameters for this work. Power Gain and delay has been studied with respect to the mention four varied parameters and also, power delay product (PDP) has been studied with respect to the supply voltage 22 nm CMOS technology has been chosen for simulating purpose. The full adder cell is one of the fundamental building blocks used in circuits like multipliers, comparators and is also used to design high-end microprocessors etc. Besides, this proposed circuit can be used as an alternative while designing RF circuits (RFID tags and Readers). The ultra-low power full adder has been studied and it can show better performance in terms of lifetime of a battery used in RFID tags. To validate the analytical data, extensive T-SPICE simulations have been performed.
