Fig 5 - available from: Journal of Hardware and Systems Security
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Since the standardization of AES/Rijndael symmetric-key cipher by NIST in 2001, it gained widespread acceptance in various protocols and withstood intense scrutiny from the theoretical cryptanalysts. From the physical implementation point of view, however, AES remained vulnerable. Practical attacks on AES via fault injection, differential power ana...
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... Figure 5, in the case of 5 power consumption curves, the average time consumption of the improved algorithm is 78.6 s, and the average time consumption of the original algorithm is as high as 370 s; while in the case of 10 power consumption curves, the average time consumption of both the improved algorithm and the original algorithm is greatly reduced. e more the power consumption curve is, the smaller the average time consumption of the algorithm is, which accords with the analysis before the experiment [31][32][33]. Computational Intelligence and Neuroscience Figure 6, it is the comparison of the average residual entropy of the algorithm. In five power consumption curves, the average residual entropy of the original algorithm is higher than that of our proposed algorithm, while the average residual entropy of the proposed algorithm is slightly higher than that of the original algorithm. ...
With the rapid development of network and communication technology, the interaction of various information data is more and more frequent, and people pay more and more attention to information security. The information encryption algorithm is a research hotspot in the field of information security. The Advanced Encryption Standard (AES) algorithm has been widely used in the field of information security with its high security and encryption efficiency. This paper mainly introduces the optimization of the AES-128 encryption algorithm of the security layer in ZigBee networking of the Internet of Things. By analyzing the principles of ZigBee networking and the AES encryption algorithm, the changes are optimized. In this paper, the new S-box cryptographic properties are used after analysis and calculation. The affine transformation period, the number of iteration cycles, and the algebraic expression of the S-box are improved. Its cryptographic properties are better than the S-box of the original algorithm, and the security of the algorithm is improved. In the theory of column hybrid algorithm, the computational complexity is reduced by changing the fixed polynomial, and the efficiency of the column hybrid algorithm is improved. In this paper, the performance of the improved AES algorithm is tested. The results show that, in the power consumption curve experiment, the recovery success rate of the original algorithm is about 42%, and the recovery success rate of the improved algorithm is nearly 60%. The improved algorithm is faster than the original algorithm in achieving a recovery success rate of 100%. Experimental results show that the design can accurately complete the encryption and decryption of the AES algorithm, and the performance is better than the original algorithm, which proves the overall superiority of the algorithm.
AES encryption algorithm is a universal algorithm, which can be used in many fields, including intelligent marketing. In the field of modern intelligent marketing, every enterprise adopts the platform model to carry out marketing activities, which gives birth to the high-tech intelligent marketing platform. The use of this platform does bring great convenience to marketing activities and effectively improve the success rate and efficiency of marketing. However, with the in-depth use of the intelligent marketing platform, people find that there are many security risks in this platform, including Marketing information may be damaged by people, indicating that the platform needs further optimization. At this time, AES encryption algorithm has become the main method of platform optimization. In order to understand the optimization performance of AES encryption algorithm in the high-tech intelligent marketing platform, this paper will analyze the concept of the algorithm, the existing defects of the platform, the optimization scheme of the platform under the algorithm, and finally simulate the results of the optimization scheme to verify the feasibility of the application of the algorithm.
Because encryption is a fundamental security building blocks, existing encryption techniques like AES, Twofish, Blowfish, Triple DES are constantly under the threat of being compromised. We introduce a simple graph-theoretic encryption method named CryptoCliqIn using clique injection and prove that the decryption of this encryption without the appropriate key is \#P-complete. We have shown that the proposed model does not introduce delays in encryption and decryption time and provides a more secure mechanism than some of the existing encryption mechanisms. Finally, an adaptation of CryptoCliqIn in an intelligent system is discussed under the intelligent and smart building setup.
Scan based DfT is indispensable for IC testing in the semiconductor chip industry to ensure correctness of chip, both functionally and structurally. Since a higher degree of fault coverage is essential, cryptographic ICs rely on it as a standard technique during manufacturing test. Yet an invaluable tradeoff needs to be met between security and testability, because it is the observability and controllability of the sequential memory elements in the scan chain which are enhanced to facilitate testing. Well designed differential scan attacks which make use of this feature can prove to be critically pervasive to leak secret keys embedded in cryptochips. Use of response compactors ensure test cost reduction. Existing differential scan attacks target Hamming weight pairs that are unique. The motivation of our work lies in the fact that carefully fabricating additional bits in order to transform a unique Hamming weight to a non-unique one, existing attacks can be defended. In this paper, we propose Co-relation scan attack (COSAA) on AES crypto-system which can work even in the presence of test response compaction. We show our attack technique to be lethal against any possible Hamming weight model which means that the designer needs to prevent the circuit under test from a relatively broader attack surface. Our experiments show the proposed attack can successfully recover the secret key of AES with XOR compaction in 24 milliseconds using an average desktop machine.
An SoC should be verified against several vulnerabilities to endure its security and trust. However, the existing verification and validation techniques are not sufficient to identify security issues in SoC due to the lack of security specification, the vast complexity of SoC designs, aggressive time-to-market, globally distributed supply chain of SoCs, design issues, and unsecured computer-aided design (CAD) tools. In this chapter, we review the challenges in SoC security and trust verification and review some existing approaches to evaluate the resiliency of SoCs against various types of attacks. We also discuss the limitation of these approaches.
Trustworthy System-on-Chip (SoC) design is vital to provide the hardware root-of-trust to enable a truly secure cyberspace. This book presented a wide variety of state-of-the-art SoC security validation and verification techniques for designing trustworthy SoCs. This chapter concludes the book with a summary of ideas presented in the previous chapters, and outlines the road map of future security validation challenges and opportunities.
Hardware Trojan detection has emerged as a critical challenge to ensure security and trustworthiness of integrated circuits. A vast majority of research efforts in this area has utilized side-channel analysis for Trojan detection. Functional test generation for logic testing is a promising alternative but it may not be helpful if a Trojan cannot be fully activated or the Trojan effect cannot be propagated to the observable outputs. Side-channel analysis, on the other hand, can achieve significantly higher detection coverage for Trojans of all types/sizes, since it does not require activation/propagation of an unknown Trojan. However, they have often limited effectiveness due to poor detection sensitivity under large process variations and small Trojan footprint in side-channel signature. In this chapter, we address this critical problem through a novel side-channel-aware test generation approach, based on a concept of multiple excitation of rare switching (MERS) that can significantly increase Trojan detection sensitivity. (1) It presents in detail a scalable statistical test generation method, which can generate high-quality testset for creating high relative activity in arbitrary Trojan instances; (2) it analyzes the effectiveness of generated testset in terms of Trojan coverage; and (3) it describes two judicious reordering methods that can further tune the testset and greatly improve the side-channel sensitivity. Simulation results demonstrate that the tests generated by MERS can significantly increase the Trojans sensitivity, thereby making Trojan detection effective using side-channel analysis.
Designing a secure cryptographic accelerator is challenging as vulnerabilities may arise from design decisions and implementation flaws. To provide high security assurance, we propose to design and build cryptographic accelerators with hardware-level information flow control so that the security of an implementation can be formally verified. This paper uses an AES accelerator as a case study to demonstrate how to express security requirements of a cryptographic accelerator as information flow policies for security enforcement. Our AES prototype on an FPGA shows that the proposed protection has a marginal impact on area and performance.
Design-for-debug structures such as trace buffers are widely used in post-silicon validation to improve the observability. Various design-for-test structures, such as scan chains, are also utilized for observability improvement. While debug engineers would like to have better observability, the security experts would like to enforce limited or no visibility with respect to the security modules. This chapter illustrates that the structures inserted for the benefit of debugging can be a source of information leakage. Specifically, this chapter describes security attacks on both design-for-debug (trace buffer) and design-for-test (scan chain) structures. Experimental results show that trace buffer attack is capable of partially recovering the secret keys of different AES implementations.
