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ADC block diagram

ADC block diagram

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Figure 1: ADC block diagram
Figure 2: ADC fault set
Figure 3 summaries some of the data obtained. The fault coverage is...
Figure 3: ADC failures Figures 4 to 8 illustrate some of the failure...
Figure 4: Non-monotonic behaviour I
A failure mode analysis of a 6-bit folding ADCs.
Chapter
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  • Jan 2001
For next generation mixed signal ICs, the integration of Design-for-Testability and Built-In Self-Test structures is expected to be of crucial importance for satisfying quality and economic demands. The judgment and evaluation of such testability optimisations, however, requires a better understanding of circuit specific failure modes in deep sub-m...
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Context 1
... analogue section of the converter comprises a resistor ladder to generate the differential reference voltages, two amplifier arrays, a track and hold array, and a comparator array, as illustrated in Figure 1. Two groups of signal paths can be identified. ...
Context 2
... first group of signals contributes to the calculation of the four lower bits, d 0 to d 3 , while the second group determines the two higher bits d 4 and d 5 . For each group the subcircuits contained in the five arrays (Figure 1) ...

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