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A typical Quantum CAD flow for ion-trap quantum circuit fabric. PMD refers to the physical machine description, which is different for different quantum circuit implementation technologies. Blocks in the dashed box identify the focus of this paper.
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Quantum computers are exponentially faster than their classical counterparts in terms of solving some specific, but important problems. The biggest challenge in realizing a quantum computing system is the environmental noise. One way to decrease the effect of noise (and hence, reduce the overhead of building fault tolerant quantum circuits) is to r...
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... to traditional computers, a CAD flow is required for quantum computers not only to streamline the design process, but also to enable design of large and complex quantum circuits. Figure 1 shows a typical CAD flow for quantum computers. The gray blocks denote optimization tasks that benefit from design automation. ...
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... For larger circuits and to allow for scalability, heuristic solutions are a better fit Lao et al. 2022;Wille et al. 2016;Guerreschi and Park 2018). Some methods proposed by related works include the use of SMT solvers (Murali et al. 2019a;Lye et al. 2015), greedy heuristic Zulehner et al. 2018;Dousti and Pedram 2012;Bahreini and Mohammadzadeh 2015), and machine learning-based algorithms (Herbert and Sengupta 2018;Venturelli et al. 2018;Pozzi et al. 2020). These solutions all focus on the "routing" part of the mapper. ...
To execute quantum circuits on a quantum processor, they must be modified to meet the physical constraints of the quantum device. This process, called quantum circuit mapping, results in a gate/circuit depth overhead that depends on both the circuit properties and the hardware constraints, being the limited qubit connectivity a crucial restriction. In this paper, we propose to extend the characterization of quantum circuits by including qubit interaction graph properties using graph theory-based metrics in addition to previously used circuit-describing parameters. This approach allows for an in-depth analysis and clustering of quantum circuits and a comparison of performance when run on different quantum processors, aiding in developing better mapping techniques. Our study reveals a correlation between interaction graph-based parameters and mapping performance metrics for various existing configurations of quantum devices. We also provide a comprehensive collection of quantum circuits and algorithms for benchmarking future compilation techniques and quantum devices.
... For larger circuits and to reach scalability, heuristic solutions are a better fit [17], [27], [31], [63]. Some methods proposed by related works include the use of SMT solvers [37], [41], greedy heuristic [4], [13], [31], [64] and machine learning-based algorithms [18], [46], [61]. These solutions all focus on the 'routing' part of the mapper. ...
Quantum circuits are widely used for benchmarking quantum computers and therefore crucial for the development and improvement of full-stack quantum computing systems. To execute such circuits on a given quantum processor, they have to be modified to comply with its physical constraints. That process is done during the compilation phase and known as mapping of quantum circuits. The result of the mapping procedure is highly dependent not only on the hardware constraints, but also on the properties of the circuit itself. In this paper, we propose to explore the structure of quantum circuits to get detailed insights into their success rate when being executed on a given quantum device while using a specific compilation technique. To this purpose, we have characterized a large body of quantum circuits by extracting graph theory-based properties from their corresponding qubit interaction graphs and afterwards clustered them based on those and other commonly used circuit-describing parameters. This characterization will help i) to perform an in-depth analysis of quantum circuits and their structure and group them based on similarities; ii) to better understand and compare the mapping performance when run on a quantum processor and, later on, iii) to develop mapping techniques that use information from both, algorithms and quantum devices. Our simulation results show a clear correlation between interaction graph-based parameters as well as clusters of circuits with their mapping performance metrics when considering the constraints of a Surface-97 processor, as well as of IBM-53 Rochester and Aspen-16 devices. In addition to that, we provide an up-to-date collection of quantum circuits and algorithms taken from well-known sources with the goal of having an all-gathering, easy-to-use, categorized and characterized benchmark set available for the quantum computing community.
... Several studies have been done on automation of different steps of the physical design process. Some researchers [6,7,[11][12][13][14][15][16] worked on the entire physical design flow and proposed techniques for each of its step while others [17][18][19][20] proposed some techniques for scheduling of a quantum circuit on a layout. Mohammadzadeh et al [21][22][23] introduced the physical synthesis concept for quantum circuits and proposed some practical physical synthesis techniques [21,[23][24][25]. ...
Developing a scalable quantum computer as a single processing unit is challenging due to technology limitations. A solution to deal with this challenge is distributed quantum computing where several distant quantum processing units are used to perform the computation. The main design issue of this approach is costly communication between the processing units. Focused on this issue, in this paper, an efficient partitioning approach is proposed which combines both gate and qubit teleportation concepts in an efficient manner to minimize the communication. Experimental results show the proposed approach on average reduces the communication cost by about 29.5% in comparison with the best approaches in the literature.
... Therefore, some of them will have to be moved or routed for which the compiler will insert a MOVE-operation for the run-time routing logic. When targeting a real or simulated quantum processor, the mapping of circuits is an important topic as described in [33,34]. The circuit description of the algorithms does not usually consider a physical location of the qubits and assumes that any kind of interaction between qubits is possible. ...
This paper presents the definition and implementation of a quantum computer architecture to enable creating a new computational device - a quantum computer as an accelerator In this paper, we present explicitly the idea of a quantum accelerator which contains the full stack of the layers of an accelerator. Such a stack starts at the highest level describing the target application of the accelerator. Important to realise is that qubits are defined as perfect qubits, implying they do not decohere and perform good quantum gate operations. The next layer abstracts the quantum logic outlining the algorithm that is to be executed on the quantum accelerator. In our case, the logic is expressed in the universal quantum-classical hybrid computation language developed in the group, called OpenQL. We also have to start thinking about how to verify, validate and test the quantum software such that the compiler generates a correct version of the quantum circuit. The OpenQL compiler translates the program to a common assembly language, called cQASM. We need to develop a quantum operating system that manages all the hardware of the micro-architecture. The layer below the micro-architecture is responsible of the mapping and routing of the qubits on the topology such that the nearest-neighbour-constraint can be be respected. At any moment in the future when we are capable of generating multiple good qubits, the compiler can convert the cQASM to generate the eQASM, which is executable on a particular experimental device incorporating the platform-specific parameters. This way, we are able to distinguish clearly the experimental research towards better qubits, and the industrial and societal applications that need to be developed and executed on a quantum device.
... Constraints (11)-(16) make sure that movement of qubits is done legally. Constraint (11) illustrates that if qubit q must move from the location of gate G i to the location of gate G i ′ , therefore qubit q must pass all the channels in the path between these two locations and then, gate G i ′ can start. Therefore the exit time of qubit q through each of these channels is prior to the execution of gate G i ′ , Constraint (12) checks this condition. ...
... Constraint (12) introduces the minimum possible value for variable U qri ; this constraint indicates that the Exit time of qubit q from channel r (after execution of gate G i ) is at least more than finishing time of gate G i plus delay of a movement. Figure 2 is used to shed light on constraints (11) and (12) in which, Gate G i is executed before gate G i ′ and after execution of gate G i qubit q must pass through channels r 1 , r 2 , r 3 , r 4 to reach the location of gate G i ′ . ...
... The delay of each gate is calculated as follows 11 : ...
In recent years, many studies have been focused on designing quantum circuits for the promising future of quantum computers. In these studies, latency has been considered as one of the main performance measures in quantum circuit design. This paper proposes a congestion‐aware mixed integer linear programming model for placement and scheduling of quantum circuits. The proposed model determines initial locations for qubits and locations for gates, and schedules the movement of qubits along the channels in such a way that the total latency is minimized. Since finding the optimal solution of the model for large circuits within a reasonable amount of time is not practical, a heuristic solution method has been developed for the proposed model. Moreover, some experiments are conducted to evaluate the performance of the proposed model and the solution approach. Experimental results show that the proposed approach improves the average latency by about 14.5% for the attempted benchmarks compared with the best in the literature.
... Approximate solutions using heuristics can be used for large quantum circuits [25], [34], [52]. Some used methods are (Mixed) Integer Linear Programming ((M)ILP) solvers [24], [39], [53], Satis ability Modulo Theory (SMT) solvers [43], [45], [46], heuristic (search) algorithms [24], [28], [31], [33], [40], [44], [54], decision diagrams [27], or even temporal planners and reinforcement learning [37], [51]. • Cost function: there are di erent metrics that can be optimised in the mapping process. ...
Quantum computing is currently moving from an academic idea to a practical reality. Quantum computing in the cloud is already available and allows users from all over the world to develop and execute real quantum algorithms. However, companies which are heavily investing in this new technology such as Google, IBM, Rigetti, Intel, IonQ, and Xanadu follow diverse technological approaches. This led to a situation where we have substantially different quantum computing devices available thus far. They mostly differ in the number and kind of qubits and the connectivity between them. Because of that, various methods for realizing the intended quantum functionality on a given quantum computing device are available. This paper provides an introduction and overview into this domain and describes corresponding methods, also referred to as compilers, mappers, synthesizers, transpilers, or routers.
... Much of this work focuses primarily on linear nearest neighbor (LNN) architectures or 2D lattice architectures as in [58,60,62,64,67]. Some work has focused on ion trap mappings as in [20] though the architecture of this style of device resembles more closely that of a 2D architecture. Some work has recently focused on optimization around specific error rates in near term machines as in [40,47]. ...
Current quantum computer designs will not scale. To scale beyond small prototypes, quantum architectures will likely adopt a modular approach with clusters of tightly connected quantum bits and sparser connections between clusters. We exploit this clustering and the statically-known control flow of quantum programs to create tractable partitioning heuristics which map quantum circuits to modular physical machines one time slice at a time. Specifically, we create optimized mappings for each time slice, accounting for the cost to move data from the previous time slice and using a tunable lookahead scheme to reduce the cost to move to future time slices. We compare our approach to a traditional statically-mapped, owner-computes model. Our results show strict improvement over the static mapping baseline. We reduce the non-local communication overhead by 89.8\% in the best case and by 60.9\% on average. Our techniques, unlike many exact solver methods, are computationally tractable.
... 1. Real qubits: When targeting a real quantum processor, the mapping of circuits is an important topic as described in [24,25]. The circuit description of the algorithms does not usually consider a physical location of the qubits and assumes that any kind of interaction between qubits is possible. ...
... Resourceintensive, physics-driven gate characterization techniques are not a scalable solution to characterizing devices and applications which are rapidly increasing in size and generally do not allow for a high level of dynamic tuning. Quantum circuit characterization methods may provide effective models of device behaviors that are efficient to generate and easy to interpret by a supporting programming environment, e.g., a compiler [28,29,30]. In particular, the validation of application behavior will require debugging methods and programming techniques that support mitigating computational errors in quantum circuits [31,32]. ...
Noisy intermediate-scale quantum (NISQ) devices offer unique platforms to test and evaluate the behavior of non-fault-tolerant quantum computing. However, validating programs on NISQ devices is difficult due to fluctuations in the underlying noise sources and other non-reproducible behaviors that generate computational errors. Efficient and effective methods for modeling NISQ behaviors are necessary to debug these devices and develop programming techniques that mitigate against errors. We present a test-driven approach to characterizing NISQ programs that manages the complexity of noisy circuit modeling by decomposing an application-specific circuit into a series of bootstrapped experiments. By characterizing individual subcircuits, we generate a composite model for the original noisy quantum circuit as well as other related programs. We demonstrate this approach using a family of superconducting transmon devices running applications of GHZ-state preparation and the Bernstein-Vazirani algorithm. We measure the model accuracy using the total variation distance between predicted and experimental results, and we find that the composite model works well across multiple circuit instances. In addition, these characterizations are computationally efficient and offer a trade-off in model complexity that can be tailored to the desired predictive accuracy.
... 1) Real qubits: When targeting a real quantum processor, the mapping of circuits is an important topic as described in [29] and [30]. The circuit description of the algorithms does not usually consider a physical location of the qubits and assumes that any kind of interaction between qubits is possible. ...
This article presents the definition and implementation of a quantum computer architecture to enable creating a new computational device-a quantum computer as an accelerator. A key question addressed is what such a quantum computer is and how it relates to the classical processor that controls the entire execution process. In this article, we present explicitly the idea of a quantum accelerator that contains the full stack of the layers of an accelerator. Such a stack starts at the highest level describing the target application of the accelerator. The next layer abstracts the quantum logic outlining the algorithm that is to be executed on the quantum accelerator. In our case, the logic is expressed in the universal quantum-classical hybrid computation language developed in the group, called OpenQL, which visualized the quantum processor as a computational accelerator. The OpenQL compiler translates the program to a common assembly language, called cQASM, which can be executed on a quantum simulator. The cQASM represents the instruction set that can be executed by the microarchitecture implemented in the quantum accelerator. In a subsequent step, the compiler can convert the cQASM to generate the eQASM, which is executable on a particular experimental device incorporating the platform-specific parameters. This way, we are able to distinguish clearly the experimental research toward better qubits, and the industrial and societal applications that need to be developed and executed on a quantum device. The first case offers experimental physicists with a full-stack experimental platform using realistic qubits with decoherence and error-rates, whereas the second case offers perfect qubits to the quantum application developer, where there is neither decoherence nor error-rates. We conclude the article by explicitly presenting three examples of full-stack quantum accelerators, for an experimental superconducting processor, for quantum accelerated genome sequencing and for near-term generic optimization problems based on quantum heuristic approaches. The two later full-stack models are currently being actively researched in our group.
