Figure - available from: Analog Integrated Circuits and Signal Processing
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A two-stage MASH sigma-delta modulator. a Conventional (an analog subtractor is required to implement the circuit). b Proposed (the analog subtractor is substituted by a digital subtractor, and second stage analyzes a purely analog waveform)
Source publication
A new technique to evaluate the quantization error of cascaded sigma-delta modulators in digital domain is presented. It avoids the complications associated with analog extraction of the quantization error in multistage noise shaping (MASH) modulators before feeding the error to the proceeding stage. Instead, the quantization error is estimated and...
Citations
... Multistage operational transconductance amplifier (OTA) in closed-loop configuration is one of the basic building blocks used extensively to buffer and amplify the voltage and current signals generated by a variety of integrated circuits (ICs), from discrete-time switched-capacitor analog-to-digital and digital-to-analog converters to continuous-time filters, low-dropout regulators (LDOs), audio amplifiers and active-matrix liquid crystal displays (LCDs), micro-electromechanical systems (MEMS), and line drivers. [1][2][3][4][5][6][7][8][9][10] Many applications falling into these categories favor an amplifier that can drive a naturally variable load capacitor (C L ) since this parameter experiences remarkable excursions during the start-up and normal operation of the OTA. In some applications, the change of C L is not significant, yet the design should be robust to C L variations. ...
Advanced multistage amplifiers suffer from load‐dependent stability issues, which limit the load capacitor range they can drive. In this work, the concept of global impedance attenuation (GIA) network is introduced to improve an amplifier's stability in the presence of significant load capacitor variations. Composed of multiple parallel resistor‐capacitor (RC) branches, the equivalent high‐frequency output impedance of gain stages is shaped by the GIA network such that a desired frequency spectrum is obtained over a wide range of load capacitor. The parasitic poles at the output of the gain stages are nullified by the proposed network, thereby simplifying the amplifier's transfer function and reducing the minimum load capacitor it can drive. The idea is applied to design a three‐stage operational transconductance amplifier (OTA) with cascode global impedance attenuation (CGIA). Small‐signal analysis shows that the OTA is stable regardless of the load capacitor, and it can drive very small to ultra‐large load capacitors. This feature is verified by the post‐layout simulations of a CGIA amplifier in 0.18‐μm complementary metal‐oxide semiconductor (CMOS) process. The core occupies a die area of 0.0053 mm2 while consuming a static current of 10.97 μA from 1.8‐V voltage supply. The unity‐feedback configuration is unconditionally stable for any load capacitor higher than 10 pF. To the best of our knowledge, this corresponds to the widest range of load capacitance reported for prior‐art three‐stage amplifiers.
... For this purpose, a high DC gain factor is achieved using cascoded MOSFETs operating with reduced quiescent current consumption (Leung and Mok 2001). Such implementation is no longer feasible in scaled CMOS where the maximum voltage supply is bounded by the gate oxide breakdown of the MOSFETs (Aminzadeh and Dashti 2019;Eschauzier and Huijsing, 2013;Aminzadeh, 2018a). Nanoscale MOS devices also suffer from reduced intrinsic g m r O gain factor, whose value is decreasing with every generation of CMOS technology. ...
Purpose
Multistage amplifiers require a reliable frequency compensation solution to remain stable in a closed-loop configuration. A frequency compensation scheme creates an inner negative feedback loop amongst different amplifying stages and shapes the frequency response such that an unconditionally stable single-pole amplifier results for closed-loop operation. The frequency compensation loop is thus responsible for the placement of the poles and zeros and the final stability of multistage amplifiers. An amplifier incorporating a sophisticated frequency compensation network cannot be, however, analyzed in the presence of a complex ac feedback loop. The purpose of this study is to provide a reliable model for the compensation loop of multistage amplifiers at the higher frequencies.
Design/methodology/approach
In this paper, the major part of the amplifier, including a two-port network comprising the compensation network, is characterized using a reliable feedback model.
Findings
The model integrates all the frequency-dependent components of the frequency compensation network, and it can evaluate the nondominant real or complex poles of an amplifier.
Originality/value
The reliability of the proposed model is verified through analysis of the frequency response of the amplifiers and by comparing the analytic results with the simulation results in standard CMOS process.
... Traditional RD modulator of MEMS digital geophone is mainly focused on using the sensing element as a low-pass filter to form a 2nd-order electromechanical RD modulator. A common sensing element is a 2nd-order mass-damper-spring mechanical system, however, the equivalent dc gain of this mechanical system is quite low, which leads to an unsatisfactory noise performance [6]. At present, in order to decrease the system noise floor and improve system performance, RD modulator all focused on applying additional electronic integrators in series with the sensing element to form the high order RD modulator [7][8][9]. ...
... Fractional-order zero-phase integrator can be designed by Eq.s (6) and (11), putting a left Grünwald-Letnikov's calculus operator D v l and a right Grünwald-Letnikov's calculus operator D v r in parallel. The basic structure of FOZPI is shown in Fig. 1. ...
In the system of MEMS digital geophone, the mechanical sensing element and post-stage detection circuit are combined to work as the Sigma-Delta (ΣΔ) modulator. The performance of ΣΔ modulator can be improved by cascading electrical integrators behind the sensitive structure. Thus, additional integrators are introduced in series with the mechanical sensing element to form the high order ΣΔ modulator. In fact, the increase of the system order of ΣΔ modulator is limited to maximum 5 or 6 order due to the system instability. In other words, the stability of ΣΔ modulator system will be weaken caused by the phase loss from the additive integrators. This paper proposes a fractional-order zero-phase integrator (FOZPI) that in series with the 5th-order ΣΔ modulator to effectively suppress the phase distortion in the noise-shaping process for MEMS digital geophone. The proposed ΣΔ modulator with the FOZPI applies in MEMS digital geophone can better enhance the compromise capability between the high signal to noise ratio (SNR) and strong robust stability than the pure 5th-order ΣΔ modulator does. The order of FOZPI is designed by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameter and further improve the noise performance. Finally, the simulation results show that the proposed ΣΔ modulator with FOZPI scheme is an effective way to improve the performance and loop stability for ΣΔ modulator.
... To increase the signal-to-quantization noise ratio, the designed CDC employs a three-order delta-sigma modulator based on a cascade of integrators with a CIFF structure. In contrast, the multi-stage noise shaping (MASH) modulators in [11]- [13] are vulnerable to mismatch effects. The currentstarved operational transconductance amplifiers (OTAs) are applied in the delta-sigma modulator's first integrator to improve its current utilization and reduce power consumption and an auto-zeroing technique is adopted for the OTAs to reduce the offset and noise. ...
This paper proposes a low-power delta-sigma capacitance-to-digital converter (CDC) for a capacitive sensor. The input of the capacitive sensor employs a zoomed-in technique with the offset capacitor to extend the input capacitance range. The proposed CDC uses a third-order switched capacitor delta-sigma modulator to provide a digital output, based on a cascade of integrators with a feed forward (CIFF) structure. The current-starved operational transconductance amplifiers (OTAs) are applied in the delta-sigma modulator's first integrator to improve the current efficiency and reduce the power consumption. An auto-zeroing technique is used in the OTAs to reduce their offset and noise. The circuit was implemented in a 0.18-μm CMOS technology and occupies an area of 0.496 mm
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. The measurable capacitance range of the CDC can be varied from 0 to 8 pF. In a measurement time of 0.8 ms, the delta-sigma CDC achieved a 12.7 effective number of bits while consuming 18.6-μA current from a 2-V supply voltage.
