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It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that...
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... ADC is a mixed-signal system with an analog front-end and a digital back-end. Conventionally, ADCs depend heavily on good analog design, namely careful matching, layout, and linear circuits. As circuits scale into deep sub- micron, designing highly linear circuit components becomes increasingly dif fi cult [1]. Therefore, an ADC architecture that can rely less on linear circuits is desirable. The most essential component of an ADC is the comparator. It is the entity that ultimately does the translating from the analog world to the digital world. The circuits upstream from the comparator tend to be highly analog, and those downstream, digital. The digital circuits amplify signals all the way to the rails, so linearity is not important, only delay matters. Due to their innately low sensitivity to noise and physical layout, digital circuits lend themselves to automated synthesis. In order to minimize analog circuit requirements, it is appropriate to begin with an architecture that is already highly digital. Since the comparator de fi nes the boundary between analog and digital realms, the fl ash ADC architecture will be considered, as it places the comparator as close to the analog input signal as possible (Fig. 1). If there is no pre-ampli fi cation, the only analog components in a conventional fl ash ADC are the analog voltage references and the comparators. Flash ADCs use a reference ladder, in some form, to generate the comparator trip points that correspond to each digital code. Typically the references are either generated by a resistor ladder [2] or some form of analog interpolation [3], but the effect is the same: a reference is generated speci fi cally for each comparator. First proposed in [4] is the stochastic ADC. A stochastic ADC eliminates an explicit reference generation and uses compara- tors’ inherent input-referred offsets due to device mismatch as the trip-points. This has been shown that this can be an effective way to eliminate the need for a reference ladder [5]–[7]. Once reference generation is out of the picture, we are left with comparators and digital logic. The remaining analog comparator, it will be shown in this paper, may also be constructed from digital blocks. For the fi rst time, this allows for the possibility that the entire ADC can be constructed using standard digital synthesis fl ows; moreover, this type of stochastic fl ash ADC can be described in Verilog code. The overall architecture is discussed in Section II. Section III discusses the operation of an analog comparator that is constructed from standard digital NAND gates. Section IV deals with how to cause the fl ash ADC to have a linear transfer function even though the sampler thresholds are distributed in a nonlinear fashion. Section V describes the speci fi cs of fabricated test chip. The results of the said test chip are presented in Section VI. II. S YNTHESIZABLE S TOCHASTIC F LASH A RCHITECTURE In a conventional fl ash ADC, the input signal is connected to the inputs of a group of comparators. The threshold of each comparator is set precisely, by some sort of reference ladder, such that all comparator thresholds are equally spaced by 1 LSB. In reality, there is also a random offset in each comparator that, in effect, readjusts each comparator threshold by a random amount. This random offset, due to device mismatches can be assumed to be a Gaussian distribution with a mean of zero and variance inversely proportional to comparator area [8]. In order to synthesize a fl ash ADC from Verilog code, there are a few key changes that must be made to the architecture. First of all, the resistor ladder must be removed. The differential input is then connected directly to the input of all of the comparators. Since there are no longer explicit voltage references, this architecture depends on the virtual voltage references that exist as comparator offsets due to random mismatch. If the mismatch is too small, then the input signal range will also be very small, so very small comparators are actually preferred. In the case of a conventional fl ash ADC, the comparator outputs after a conversion can be expected to be a thermometer code since the comparator thresholds are monotonically increasing by design. Since comparator thresholds are random in a stochastic ADC, the order of the comparator outputs can also be expected to be random. The total number of comparators that evaluate high will still be monotonically increasing with an increase in the input voltage. Therefore a ones adder is required to sum the comparator outputs. Finally, the raw output of the comparator outputs will be distorted by the non-uniform distribution the comparator offsets. A block is then required to un-distort the signal by passing it through the inverse function of the offset distribution. Section IV discusses this in detail. The block diagram of this architecture is shown in Fig. 2. III. A NALOG C OMPARATOR FROM D IGITAL C ELLS Upon observation, the schematic of the transistors inside a CMOS NAND3 gate closely resemble half of a clocked analog comparator (Fig. 3). By connecting two NAND3 gates together as in Fig. 4, an analog-input comparator is created if the common-mode of the input is high enough to ensure that the PMOS transistors connected to the input are in the cutoff region of operation. When the clock is low, both outputs are reset to the positive supply rail. When the clock goes high, the outputs will begin to discharge through the three series NMOS devices. The discharge rate depends on the capacitance on the output node and the current through the three series devices. Since one of the series devices is connected to the analog input, the discharging current is proportional to the input. Once one of the outputs discharges to below a PMOS threshold voltage, the cross-coupled connection creates positive feedback that causes the comparator to force the outputs all the way to the supply rails. Implementing such a comparator can be done by explicitly referencing the standard library cells in the RTL Verilog code as in Fig. 5(a). In this example, a static SR-latch is added to the output of the comparator. The SR-latch holds the output data valid while the comparator is reset. The SR-latch input is buffered with inverters to reduce a memory-effect on the comparator due to the SR-latch. Although this circuit is inherently compatible with digital synthesis, the synthesizer will assume that the circuit is actually a digital one, and will try and optimize it by replacing some of the gates or changing the circuit entirely while maintaining the same digital function. This digital optimization may render the circuit nonfunctional from an analog perspective, so here the synthesis directive set_dont_touch comparator , or equivalent, will prevent the synthesizer from altering the comparator module. IV. G AUSSIAN D ISTRIBUTION M APPED TO A U NIFORM D ISTRIBUTION The probability density function (PDF) of random comparator offset is in fl uenced by many factors such as random variation of threshold voltage and current factor [9]. The Cen- tral Limit Theorem indicates that since comparator offset is a sum of independent random variables with fi nite mean and variance the PDF will be approximately Gaussian [10]. When a ramp signal is applied to the input of a stochastic fl ash ADC, the output will follow the cumulative distribution function (CDF) of comparator offset; therefore, the voltage transfer function of a stochastic fl ash ADC is the CDF of the random comparator offset. The number of comparators in the stochastic fl ash ADC must be enough such that the actual transfer function resembles the comparator offset CDF to the desired degree. To calculate the number of comparators required for a desired effective bits, let us consider an ADC with random comparator thresholds with a uniform distribution. Let us say that there are comparator thresholds within the range 0 to 1, and the number of thresholds within the range 0 to (where is value between 0 and 1) is equal to . This implies that the remaining thresholds within the range and 1 are equal to . For a random uniform distribution of , the random variable is a binomial distribution [11] with a probability mass function (PMF) ...
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Citations
... Several standard-cell-based circuits, such as Operational Transconductance Amplifiers (OTAs) [32]- [38], comparators [39]- [47], and filters [48], [49], have been proposed in the literature, demonstrating the effectiveness of the standard-cell approach in increasingly constrained analog and mixed signal integrated circuits operating in ULV conditions. Despite the ability of standard-cell-based topologies to operate at supply voltages as low as 0.15 V [36], [41], it is important to note that their performance is greatly affected by PVT variations. ...
... Several standard-cell-based comparators have been recently proposed in the literature, demonstrating state-of-theart performance in terms of power consumption and delay [39]- [44], [50]. For example, in [39], a fully synthesizable comparator based on 3-inputs NAND gates (NAND-3) was proposed. ...
... Several standard-cell-based comparators have been recently proposed in the literature, demonstrating state-of-theart performance in terms of power consumption and delay [39]- [44], [50]. For example, in [39], a fully synthesizable comparator based on 3-inputs NAND gates (NAND-3) was proposed. The main limitation of this comparator is its nonrail-to-tail input common-mode range (ICMR), which, due to the usage of NAND-3 gates, is not able to operate for low input common mode voltages, and starts to degrade its performances for input common mode voltages lower than V DD /2. ...
In this paper a novel ultra-low voltage (ULV) standard-cell-based comparator which provides rail-to-rail input common-mode range (ICMR) is presented. The topology, unlike the others in the literature, uses only 2-inputs NAND gates and is able to operate with supply voltages as low as 0.15V. A detailed theoretical analysis based on transistor level modeling is provided to explain the operating principle and highlight the performance advantages of the proposed comparator. The circuit has been tested through several simulations, including corner analysis and Monte Carlo runs, by using three different technologies: 180 nm, 130 nm and 28 nm for both a supply voltage of 0.3 V and 0.15 V. The results found not only confirm the robustness of the proposed comparator, but also demonstrate very advantageous performances. Indeed, for the same technology node it exhibits the highest speed and the lowest EDP (about ten times lower than the one of the others standard-cell-based comparators in the literature). It exhibits also the lowest power consumption and silicon area.
... Another approach is to radically rethink analog functions in digital terms [6,7], using only digital circuits, such as a class D amplifier [8]. VCO-based amplifiers [9][10][11], voltage-to-time converters [12,13], charge amplifiers [14], analog-to-digital [15][16][17][18][19] and digital-to-analog converters [20], digital voltage references [21], low-dropout regulators (LDO) [22], hybrid analog-digital amplifiers [23] and digital-based amplifiers [24][25][26][27][28][29][30][31][32] have been reported in the literature. In [24][25][26][27][28][29][30][31][32], a differential amplifier, composed of only logic gates, was proposed. ...
Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided.
... The latched comparator is a key building block for many mixed-signal applications, and finds wide diffusion in systems such as analog-to-digital converters (ADCs), wireline receivers, memory bit-line detectors and digital low-dropout regulators (DLDOs) [3,[7][8][9][10][11]. The comparator is usually composed of an input preamplifier followed by a latch, often combined in the StrongARM topology [12][13][14], where a clocked transconductor drives a pair of cross-coupled inverters by their sources or, in the double-tail topology [15][16][17][18], where the clocked preamplifier and the latch use separate tail current branches. ...
... Following the above-described context, research trends are towards designing analog blocks using digital standard cells, either to mimic the behavior of analog building blocks [29][30][31][32][33][34] or by implementing analog functions in the digital domain [7,9,10,[35][36][37][38][39][40][41][42][43][44][45][46][47][48][49]. A standard-cell-based implementation of analog functions simplifies the portability of designs among different technologies, and the speed vs. supply voltage reconfigurability. ...
... The usual approach to design standard-cell-based latched comparators starts from a NAND-based [3,[6][7][8]46] or NOR-based latch [50,51], and several designs have been presented in the literature to optimize different performances for applications in ADCs and LDOs [9,10,49,[52][53][54][55][56][57]. However, such applications typically focus on different performance parameters, hence proposed designs are not always easy to compare. ...
This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.
... In [13] a fully synthesizable comparator based on 3-input NAND gates (NAND-3) was proposed. However, the design has a limited input common mode voltage due to the use of NAND gates. ...
... In contemporary cutting-edge integration technologies, the conventional analog design that relies on amplitude-domain information representation encounters progressively harder-to-surmount obstacles. As mentioned in [2], circuit design encounters numerous challenges, such as reduced intrinsic device gain, noise, aggravated device mismatch, lower supply voltage, decreased signal swing, and manufacturing deviations. When transitioning to smaller technologies, these challenges complicate signal processing in the amplitude domain, particularly for complex mixed-signal systems such as ADC [1][2][3][4]. ...
... As mentioned in [2], circuit design encounters numerous challenges, such as reduced intrinsic device gain, noise, aggravated device mismatch, lower supply voltage, decreased signal swing, and manufacturing deviations. When transitioning to smaller technologies, these challenges complicate signal processing in the amplitude domain, particularly for complex mixed-signal systems such as ADC [1][2][3][4]. ...
... State-of-the-art designs aim to tackle the challenges associated with analog-to-digital converters (ADCs); various structures have been proposed in the literature. An instance of this is the synthesizable stochastic flash ADC architecture, which necessitates a significant amount of resources to execute, such as 3840 comparators to achieve 5.3 bits of resolution [1,2]. In [5], the researchers suggested a structure for a 4-bit ADC that uses memristors, along with a trainable artificial neural network (ANN) calibration. ...
In contemporary devices, the number and diversity of sensors is increasing, thus, requiring both efficient and robust interfacing to the sensors. Implementing the interfacing systems in advanced integration technologies faces numerous issues due to manufacturing deviations, signal swings, noise, etc. The interface sensor designers escape to the time domain and digital design techniques to handle these challenges. Biology gives examples of efficient machines that have vastly outperformed conventional technology. This work pursues a neuromorphic spiking sensory system design with the same efficient style as biology. Our chip, that comprises the essential elements of the adaptive neuromorphic spiking sensory system, such as the neuron, synapse, adaptive coincidence detection (ACD), and self-adaptive spike-to-rank coding (SA-SRC), was manufactured in XFAB CMOS 0.35 μm technology via EUROPRACTICE. The main emphasis of this paper is to present the measurement outcomes of the SA-SRC on-chip, evaluating the efficacy of its adaptation scheme, and assessing its capability to produce spike orders that correspond to the temporal difference between the two spikes received at its inputs. The SA-SRC plays a crucial role in performing the primary function of the adaptive neuromorphic spiking sensory system. The measurement results of the chip confirm the simulation results of our previous work.
... Standard-cell-based comparators have been reported operating down to 0.15 V supply, and are, therefore, a suitable alternative to analog circuits for ULV operation. The simplest latched comparator can be implemented using cross-coupled 3-input NAND gates [57]. This configuration provides a very compact comparator but with a limited ICMR, therefore, architectures that pair both NAND and NOR gates as input cells [36,[58][59][60], or are based on AND-OR-INVERTER (AOI) gates [61], have been proposed to achieve a rail-to-rail ICMR, at the cost of higher complexity and area footprint. ...
In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors' gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low V DD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at V DD = 0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at V id = 1 mV.
... The situation is quite different for analog circuits. In fact, the reduction of the supply voltage below 0.5V, combined with the reduced intrinsic gain of MOS transistors implemented in modern deep submicron technologies [4], [5], makes it very hard to meet design goals of analog circuits, and solutions where analog functions are implemented taking advantage of true digital circuits have been proposed in the literature [6], [7]. ...
This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002
mm
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, and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.
... A fully synthesizable dynamic voltage comparator was proposed by Weaver et al. in [19]. As depicted in Figure 7, the circuit relies on a two cross-coupled 3-input digital NAND gates and, when two NANDs are connected, assuming that the common-mode voltage of the input signal is high enough to cut off the input PMOS devices, an analoginput comparator is created. ...
... GATE-based comparator proposed by Weaver et al.[19]. ...
In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated FoMWalden is close to 16.2 fJ/conv.-step.
... It is mainly due to the lower supply voltage and decreased capacitance value. On another side, many challenges imposed on the circuit design, e.g., lower supply voltage, decreased signal swing, manufacturing deviations, reduced intrinsic device gain, noise, and aggravated device mismatch [187], which complicities the signal processing in amplitude domain. Especially the complex mixed-signal system such as ADC faces the mentioned challenges when migrating to the smaller technology [186][187][188][189]. ...
... On another side, many challenges imposed on the circuit design, e.g., lower supply voltage, decreased signal swing, manufacturing deviations, reduced intrinsic device gain, noise, and aggravated device mismatch [187], which complicities the signal processing in amplitude domain. Especially the complex mixed-signal system such as ADC faces the mentioned challenges when migrating to the smaller technology [186][187][188][189]. ...
... Several ADCs structures are introduced in the literature to address and attempt to overcome these challenges. One example is synthesizable stochastic flash ADC architecture, which requires many resources to implement, e.g., 3840 comparators for 5.3 bits of resolution [186,187]. However, stochastic ADCs still use amplitude-coded signals that face challenges in advanced node CMOS technology. ...
The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.
... Stochastic flash ADCs improve the linearization of the conversion by further increasing the number of comparators and adding an interpolation circuit at each digital channel. They are mixed-signal circuits that are usually implemented on custom CMOS integrated circuits [26] (8190 comparators, 6.2 ENOB, 100 MSPS) or synthesized on standard cells [27] (2040 comparators, 5.2 ENOB, 320 MSPS), [28] (2047 comparators, 5.7 ENOB, 210 MSPS). Nevertheless, flash ADCs are not suitable on FPGAs due to the large number of required external comparators and I/O connections. ...
... The distributed duty cycle PWM can be combined with the paralleled PWM and the DDR optimizations to enhance the f Sampling of the ADC. Combining the DDC-PWM and the DDR-PWM, Equation (27) is modified to Equation (28), which can be used to increment the f Sampling by augmenting the f C of the filter. ...
The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.
