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This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35¿m CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840¿W, respectively....
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Context 1
... earlier work [8], transmission function theory was used to build a full adder formed by three main logic blocks: a XOR-XNOR gate to obtain B A ⊕ and B A ⊕ signals (Block 1), and XOR blocks or multiplexers to obtain the SUM (So) and CARRY (Co) outputs (Blocks 2 and 3), as shown in Figure 1. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. ...
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... the proposal presented in [8], several papers have introduced new full adder cells by trying on different realizations for the three logic blocks shown in Figure 1. Chronologically, some of them are: 14TA [9], 14TB [10], wu_ng [11], 16T [12], 10TA [13], 10TB [14], full_rest [15], mux_based [16], and wey_chow [17]. ...
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... a deep comparative study presented in [18], the most efficient realization for block 1 was extracted: the one implemented with SR-CPL logic style. But another important conclusion was pointed out over there: the major problem on regards of propagation delay for a full adder built upon the logic structure shown in Figure 1, is that it is necessary to obtain the B A ⊕ and B A ⊕ intermediate signals, which are then used to drive other blocks in order to generate the final outputs. Thus, the overall propagation delay and, in most of the cases, the power consumption of the full adder, depend on the delay and voltage swing of the B A ⊕ and B A ⊕ signals, generated within the cell. ...
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... the other hand, the full adders designed upon the logic structure shown in Figure 1 (bay_10a, bay_10b, bay_14a, bay_14b, bay_16, full_rest, tran_funct, wey_chow) have larger propagation delays (around or exceeding 1 ns) as expected, due to the internal XOR/XNOR gates that generate intermediate signals having an extra delay, used to control the output blocks. ...
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Citations
... Basava et al. proposed a one-bit adder design with transmission gate logic (TGL) of CMOS logic with direct and reverse polarisation logic in 180 nm processing. The full adder requires 16 transistors which consume 12.63nW of power with a critical delay of 16.68 ns [1]. Kandpal et al. modified the XOR-XNOR structure with 10-transistor designs and utilised it to construct a full adder. ...
The general focus of this work is to design an area-optimised full adder and utilise it to lay out a low-power arithmetic unit that can be helpful for microprocessors. A traditional full adder with 28 transistors has been devised with 10 transistors of an equal amount of PMOS and NMOS, guaranteeing the proper switching activity. The proposed full adder has one XOR gate and two 2:1 multiplexers in which the XOR gate has been customised with 4 transistors using pass transistor logic (PTL). In contrast, the gate diffusion input (GDI) technique has been used to alter the multiplexer design. The combination of the GDI and PTL brings a novelty to the full adder circuit, through which the design required only 10 transistors to perform adding operations. The proposed full adder design has been constructed against ten different complementary metal oxide semiconductor processing technologies, namely 0.6 µm, 0.8 µm, 0.12 µm, 1.2 µm, 0.18 µm, 0.25 µm, 0.35 µm, 50 nm, 70 nm and 90 nm. Pre- and post-layout simulations evidence the accuracy of the results in which the design consumes 1.843 µW of power with 0.605 ns as the worst-case delay on 90 nm technology. Further, the full adder has been extended as an adder/subtractor unit of 4 bits, with the power delay product as 0.1285 × 10− 18 J for the critical delay of 1.095 ns. The proposed design has been compared against the various full and approximate adders. The full adder has a 12.99% power reduction over the existing low-power adder and a 58.4% power reduction over the 28 transistors. This ensures that the proposed adder outperforms the traditional design and the state of the artwork.
... The comparative study among a total of 14, 1-bit FA cell [3][4][5][6][7][8][9][10][11][12] is done at 2 stages viz., standalone level, and benchmarking level, with respect to power, delay, and PDP design metrics. The standalone level observations leading to certain claims for all the 1-bit adders reported till date, needs further validation at higher architecture levels. ...
We propose a full adder (FA) circuit and compare its performance metrics with the performance metrics of 13 other 1-bit FA circuits reported till date. In comparison with all 13, 1-bit adder cell architectures, the proposed 1-bit adder cell architecture (labelled AL-31) is better by 10% in power delay product (PDP) over one of the 13 other cell architectures (labelled TGA), when used in a 32-bit ripple carry adder (RCA) benchmark circuit. But the TGA cell is having best PDP among all the 14, 1-bit cell architectures, when simulated standalone. To calculate the PDP parameter, the performance metrics under consideration are worst-case delay, and worst-case power. The work in this paper shows that the proposed 1-bit FA is a better choice for implementing long word adders. This study is based on Cadence's Spectre simulation using generic 90nm Process Design Kit (PDK). All the standalone 1-bit FA cells and their corresponding 32-bit RCA based benchmarking are done at a supply voltage V DD = 1.2V, with at least 2fF loading at their outputs.
... The truth table of the first proposed design is shown in Table I. The exact Cout can be generated according to (5) [32]. This equation suggests that Cout, only needs two simple functions (one AND function and one OR function) to be generated. ...
Approximate computing aims to reduce the power consumption and design complexity of digital systems with the cost of a tolerable error. In this paper, two ultra-efficient magnetic approximate full adders are presented for computing-in-memory applications. The proposed ultra-efficient full adder blocks are coupled with a memory cell based on magnetic tunnel junction (MTJ) to allow for nonvolatility. Therefore, they can be power-gated when required. Both of the proposed full adders have simple designs and are energy-efficient. Instead of introducing dedicated write-driver and read circuits, the restorer latch inverters are utilized to contribute to the read and write operations, which results in a lower complexity. The peripheral circuitries are designed based on the gate- all- around carbon nanotube field-effect transistor (GAA-CNTFET). The hardware simulation results show a 5.2 times improvement (78% reduction) in PDP (power-delay product), on average, when compared with the previous fully nonvolatile approximate full adders. Utilizing the approximate adders in Gaussian filters to denoise a noisy image revealed that our proposed adders result in almost the same image quality as an accurate adder. Both of our adders have an accurate carry output and two erroneous sum outputs. Nevertheless, these two erroneous outputs have a low value gap, which results in higher quality in image processing applications. The results indicates that the proposed designs make an effective trade-off between energy and accuracy, which is the main goal of approximate computing.
... Hybrid full adders use the benefits of various logic styles and are designed to reduce the transistor count while maintaining the high performance of the circuit. Hence, the most suitable adder to be used in the chain structure for designing ALU architecture is a hybrid CMOS full adder which is used in the electronic devices to achieve high speed, low power and long battery lifespan [13][14][15][16]. When it comesto battery operated devices, then speed and power dissipation both are important concerns [21][22][23]. ...
: In the recent era, voltage reduction procedure is gaining most attention for achieving minimum energy consumption. Full adder is the primary computational arithmetic block in numerous of the computing executions and hence is the critical component of ALU.Various existing full adders proposed in literature fail to accomplish low power delay product (PDP) and lacks driving strength when used in chainsstructure.In this paper two new hybrid full adders have been proposedwith an aim to achieve low PDP.Further the paper proposesripple carry adder (RCA) in chainstructure using triplet design approach to improve the driving strength. Fivedifferent hybrid full adders topologies have been implementedto build 4-bit RCA adder in regular and triplet logic design and PDP improvement is obtained in triplet design approach. All the simulations are done on 45nm technology and performance analysis done over the voltage range 0.6 V to 1.2V in Cadence Virtuoso simulation software. Simulation results are obtained to show that delay and PDP has improved in triplet designing and the proposed hybrid adders represents least PDP among other implemented reference circuits.
... In recent years mobile communication is the fast growing technology which widely uses addition for its computation [1]. The operation like multiplication, subtraction, division, address generation and many other operations uses addition in direct or indirect form [2]. In electronics, the digital circuit which performs addition is commonly known as adder. ...
... Simulations for FA designs are carried out using test-bed [2,4,10,13] shown in Fig. 1(b). Where, Win p and Win n are the widths of PMOS and NMOS transistors of the input inverters, respectively. ...
The demand for low power CMOS VLSI circuit design is increasing due to the ever-increasing demand for portable devices. A Full Adder (FA) is the basic building block of many VLSI subsystems, and it affects the performance of VLSI subsystems. The Transmission Gate (TG) and hybrid CMOS FA designs can achieve low Power Delay Product (PDP) compared to other FA designs, hence these FA designs are suitable for portable devices. A large number of repetitive simulations are required for thorough characterization of the FA design. A method to develop the mathematical model (based on 2nd degree polynomial equation) of the FA is proposed here, which satisfactorily estimates the Power Delay Product (PDP) of TG and hybrid CMOS FAs for non-simulated parameter combinations within given parameter range. Main aim of proposed method is to reduce characterization effort by estimating PDP using mathematical model, rather than estimating it through simulation. Also, mathematical model can be used to estimate the transistor widths to achieve low PDP for particular operating condition. Further, the effect of individual polynomial term, number of parameters, and number of points per parameter, on the accuracy of mathematical model is also studied.
... These modules are used for many arithmetic operations, like as addition, subtraction [1]. Thus, these facts of view, the design of a full-adder circuit are having low-power-dissipations, lower the delay, and highspeed performance [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. Many researchers are emphasizing on circuit performance through the minimum level of transistor count. ...
... Several existing papers have been illumined about the optimization of 1-bit full-adders (F-A) cell, which are trying various logic styles, XOR & XNOR gate, XOR-XNOR circuit, complementary pass-transistor-logic (CPTL) and multiplexer [3], [4], [5]. Comparative studies to design the implementation for block 1 were presented in [6]. In the block 1 modified the XNOR-XOR circuit for F-A made with the logic showing in fig.2 fig.2 [2]. ...
... The hybrid FA 1,2 herein called as Hybrid-1 FA has the advantage of good driving capability and better noise margin due to combination of pass transistor and static CMOS style of design, but they are observed to have relatively higher power dissipation due to glitches associated with the internal node capacitances and increased silicon area due to di®erent sizes of pMOS and nMOS transistors. The \double-pass-logic" (DPL) and \swing-restoring-complementary-pass-transistorlogic" (SRCPL) 14,15 based adders are having advantages of both low power and high speed but they su®er from large silicon area due to higher TC. The recently reported 1-bit FA 16 herein called as Hybrid-2 is having advantage of low power, high speed, and low TC. ...
... In the schematic of Fig. 3(a), the W =L ratios of the nMOS/pMOS transistors are indicated next to each transistor. The transistor sizing methodology as suggested in the earlier reports 15,18 has been adopted. ...
A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118(Formula presented.)(Formula presented.)W, with a delay of 606 ps, with an area of 33.1(Formula presented.)(Formula presented.)m², resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage (Formula presented.)(Formula presented.)V, input signal frequency (Formula presented.)(Formula presented.)MHz is used. This 1-bit FA is designed and implemented using Cadences’ 90(Formula presented.)nm “generic-process-design-kit” (GPDK).
... The simulation of this circuit is done using Cadences' Spectre simulator. This architecture is referred herein as 'alternative logic-3' (AL-3) as an alternative to 1-bit adder circuits, recently reported in [6,7], called herein as 'alternative logic -1' (AL-1) and 'alternative logic-2' (AL-2), discussed in subsequent sections. We simulated and compared the performance metrics, such as worst case delay, and worst case power, and worst case PDP for AL-1, AL-2, and AL-3 circuits. ...
... XOR-XOR based, XNOR-XNOR based, and XOR-XNOR based [1,2] depending upon the circuit approach to realize the two outputs: sum-S i, and carry-C i+1 . The mixed logic style architectures AL-1 and AL-2 reported in [6,7], and AL-3 proposed in this paper, together classified as another (4 th ) category, herein. The AL-1 and AL-2 architectures have been realized based on double pass logic (DPL) and CMOS transmission gate logic, resulting in mixed logic style implementation, whose block diagram and circuits are given in Fig. 1 and discussed in subsequent subsection. ...
... The proposed adder architectures are based on the truth table shown in Table l; examining the truth table it can be observed that carry out (C i+1 ) is equal to (A i .B i ) value when carry in (C i ) equal to '0' and (A i +B i ) when carry in (C i ) is equal to '1'. Thus carry out (C i+1 ) can be generated by multiplexing Boolean functions (A i .B i ) and (A i +B i ) [6,7]. In addition to evaluating C i+1 in this approach, we propose the generation of sum (S i ) also by multiplexing A i .B i .C i and A i +B i +C i using C i+1 as the select signal, i.e., sum S i is equal to A i .B i . ...
This paper discusses a rail to rail swing, mixed logic style 1-bit 28-transistor (28T) full-adder, based on a novel architecture. The performance metrics: power, delay, and power delay product (PDP) of the proposed 1-bit adder is compared with other two high performance 1-bit adder architectures reported, till date. The proposed 1-bit adder has a 50% improvement in delay, and 49% improvement in power-delay-product, over the two reported architectures, verified at 90nm technology. The power performance of proposed 1-bit adder and that of the two reported architecture are comparable, within 8%. This analysis has been done at supply voltage VDD = 1.2V, load capacitance CL=150fF, and at a maximum input signal frequency fMAX=200MHz. Also, the worst case performance metrics of the proposed 1-bit adder circuit is seen to be less sensitive to variations in VDD and CL, over a wide range from 0.6V to 1.8V, and from 0fF to 200fF, respectively
... Again, Ci can be used to select the respective value for the necessary condition, driving a multiplexer. Hence, an alternative logic scheme to design a full-adder cell can be formed by a logic block to obtain the A B and A B signals, another block to obtain the A.B and A+B signals, and two multiplexers being driven by the C input to generate the Sum and Co outputs, as shown in Figure 1 [13]. The characteristics and benefits of this logic structure are as follows. ...
... As per the results obtained in [13], three new full-adders have been designed using the logic styles DPL and SR-CPL, and a new pass-transistor logic structure is presented in Fig. 4. ...
