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Often modern designs contain regions where the implementation of
certain components is not (fully) known. These regions are called black
boxes in the following. They occur e.g. if different designers work on a
project in parallel or if IP cores are used. An approach based on a
symbolic representation of characteristic functions for verifying
circui...
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Citations
... If a full system model is required, for instance for validation or verification tasks, black box models [Günth00] are used as substitutes to hide or approximate yet unknown implementation details. Depending on the particular design component and model, the black box may produce unknown values at some or all of the outputs of the component. ...
The exponential growth in digital VLSI design scale and complexity has been enabled by comprehensive adoption of design automation tools. In the digital domain, design automation from design entry over synthesis, validation, verification to test preparation is based on reasoning about logic functions and their manipulation.
Limited knowledge about the circuit behavior may require that nodes in the circuit are modeled as having an unknown value, for instance when using incompletely specified design models. Circuit nodes also need to be modeled as unknown if their values cannot be controlled during operation or test, or if their value during operation is not known at the time of modeling.
To reflect such unknown values in design automation tools, the algorithms typically employ logic algebras with a special symbol X denoting the unknown value. However, the reasoning about functions based on such algebras results in an overestimation of unknown values in the model, and an accurate or optimal solution cannot be found. This pessimism in presence of unknown values causes additional costs at different stages of the design and test process and may even reduce product quality.
This work proposes novel, efficient approximate and accurate algorithms for the analysis of the behavior of digital circuits in presence of unknown values. Heuristics and formal Boolean reasoning techniques are combined to achieve short runtimes. The algorithms allow accurate logic and fault simulation as well as accurate automatic test pattern generation in presence of unknown values. The implications to the overhead and effectiveness of design-for-test structures are studied. The proposed algorithms are the first to completely overcome the pessimism of conventional algorithms found in todays VLSI design automation tools also for larger circuits.
Experiments on benchmark and industrial circuits investigate the pessimism in conventional algorithms and show the increased accuracy achieved by the proposed algorithms. The results demonstrate the benefits of approximate and accurate reasoning in different applications in the VLSI design process, especially in the test automation domain.
... In this paper, we consider the test generation for the fully specified portions of the circuit including unspecified variable assignments. Testing and design verification in the presence of unknowns have been studied by many researchers3456 . Günther and Drechsler [5] and Scholl and Becker [6] presented BDD-based symbolic simulation methods, which potentially suffer from memory explosion and thus have difficulties to verify large designs. ...
... Testing and design verification in the presence of unknowns have been studied by many researchers3456 . Günther and Drechsler [5] and Scholl and Becker [6] presented BDD-based symbolic simulation methods, which potentially suffer from memory explosion and thus have difficulties to verify large designs. Moreover, these methods have limited exactness and capabilities for error detection. ...
ATPG for very large scale integrated circuit designs is an important problem in industry. With the advent of SOC designs, testing and verification of the core-based designs become a challenging problem. This paper presents an algebraic test generation algorithm with unspecified variable assignments. Given a stuck at fault of the circuit with unspecified signals, the proposed algorithm uses a new encoding scheme for unspecified variable assignments, and solves the Boolean satisfiability formula representing the Boolean difference to obtain a test pattern. Experimental results demonstrate the efficiency and feasibility of the proposed algorithm.
... Model Checking of Blackbox Designs A first attempt for combinational equivalence checking of incomplete designs was made in [7] and further extended in [8]. In the context of symbolic CTL model checking, it turned out in [4] that modelling blackboxes by non-deterministic inputs ends up in ambiguous results when using different symbolic model checkers, e.g. ...
Abstract In this paper we will present an optimized structural 01X-SAT-solver for bounded,model checking of blackbox designs that exploits semantical knowledge,regarding the node selection during SAT search. Experimental results show,that exploiting the problem,structure in this way speeds up the 01X-SAT-solver considerably. Additionally, we give a concise first-order formulation that is more ex- pressive than using 01X-logic. This formulation leads to hard-to-solve QBF formulas for which experimental results from the QBF Evaluation 2006 are presented.
... Wolfgang Gunther et al. [2] presented an approach for verifying designs with black boxes, it uses BDD as its main data structure, then compares both characteristic functions of the specification and implementation. Here, we use SAT-based algorithm for Boolean comparison. ...
Error diagnosis is becoming more difficult in VLSI circuit designs due to the increasing complexity. In this paper, we present an algorithm based on verification for improving the accuracy of design error diagnosis. This algorithm integrates three-valued logic simulation and Boolean satisfiability (SAT). It uses test patterns generated by a gate level stuck-at fault ATPG tool for parallel pattern simulation, and uses SAT-based Boolean comparison to enhance the three-valued simulation, in which universally quantified conjunction normal formulas (CNF) represent the unknown constraints in the implementation with black boxes, and does not need circuit structural transformation. Our approach can quickly and efficiently eliminate many false candidates, experimental results on ISCAS'85 circuits show the accuracy and the speed of this approach.
... Wolfgang Gunther et al. [2] presented an approach for verifying designs with black boxes, it uses BDD as its main data structure, then compares both characteristic functions of the specification and implementation. Here, we use SAT-based algorithm for Boolean comparison. ...
Error diagnosis is becoming more difficult in VLSI circuit designs due to the increasing complexity. In this paper, we present an algorithm based on verification for improving the accuracy of design error diagnosis. This algorithm integrates three-valued logic simulation and Boolean satisfiability(SAT). It uses test patterns generated by gate level stuck-at fault ATPG tool for parallel pattern simulation, and uses SAT-based Boolean comparison to enhance the three-valued simulation, in which universally quantified conjunction normal formulas (CNF) represent the unknown constraints in the implementation with black boxes, and need not circuit structural transformation. Our approach can fast and efficiently eliminate many false candidates, experimental results on ISCAS?85 circuits show the accuracy and the speed of this approach.
... Recently, the problem of 'Black Box Equivalence Checking', which occurs when the specification is known, but only parts of the implementation are finished or known, has been addressed [14,12,26]. Parts of the implementation which are not finished or known are put into 'Black Boxes'. ...
... The paper is structured as follows: In Section 2 we give some preliminaries. The following section defines the problem of equivalence checking for implementations with Incompletely Specified Boxes, compares the notion of equivalence for implementations with IS-Boxes to the notion of equivalence for implementations with Black Boxes [14,12,26], and finally, it points out the relationship between our problem and the computation of satisfiability and observability don't cares. In Section 4 we present our solution to the problem. ...
... Before presenting an algorithm for equivalence checking we look into the relationship between the equivalence checking problem for implementations with IS-Boxes and the equivalence checking problem for implementations with Black Boxes [14,12,26]. ...
We consider the problem of checking whether an implementation which contains parts with incomplete information is equivalent to a given full specification. We study implementations which are not completely specified, but contain boxes which are associated with incompletely specified functions (called Incompletely Specified Boxes or IS-Boxes). After motivating the use of implementations with Incompletely Specified Boxes we define our notion of equivalence for this kind of implementations and present a method to solve the problem. A series of experimental results demonstrates the effectiveness and feasibility of the methods presented.
... When specification and implementation are structurally similar, correspondences between internal nodes can be used to simplify the verification problem [17,27,23,19,8,26]. Recently, the problem of 'Black Box Equivalence Checking', which occurs when the specification is known, but only parts of the implementation are finished or known, has been addressed [16,14,29]. Parts of the implementation which are not finished or known are combined into 'Black Boxes'. ...
... The paper is structured as follows: In Section 2 we give some preliminaries. The following section defines the problem of equivalence checking for implementations with Incompletely Specified Boxes, compares the notion of equivalence for implementations with IS-Boxes to the notion of equivalence for implementations with Black Boxes [16,14,29], and finally, it points out the relationship between our problem and the computation of satisfiability and observability don't cares. In Section 4 we present our solution to the problem. ...
... Before presenting an algorithm for equivalence checking we look into the relationship between the equivalence checking problem for implementations with IS-Boxes and the equivalence checking problem for implementations with Black Boxes [16,14,29]. At first sight the equivalence checking problem for implementations with Black Boxes seems to be a special case of the corresponding problem for IS-Boxes, since Black Boxes are boxes of which we do not know anything, i.e., they can be modeled by incompletely specified functions where the domain is empty. ...
We consider the problem of checking whether an implementation which contains parts with incomplete information is equivalent to a given full specification. We study implementations which are not completely specified, but contain boxes which are associated with incompletely specified functions (called Incompletely Specified Boxes or IS--Boxes). After motivating the use of implementations with Incompletely Specified Boxes we define our notion of equivalence for this kind of implementations and present a method to solve the problem. A series of experimental results demonstrates the effectiveness and feasibility of the methods presented.
... The present paper deals with algorithms for equivalence checking of partial implementations under the assumption that a combinational circuit is given as specification and also all implementations and Black Boxes are of combinational nature. First methods to handle this problem have been proposed in [10,9]. While these papers provide algorithms to find errors, it is not clear which errors and how many of the potential errors are detected. ...
... Our algorithms need different amounts of resources (space and time) and differ from their accurateness: They range from a simple algorithm using symbolic simulation for an approximation of the solution to an exact solution of the problem. Thereby the methods given in [10,9] are classified too. Approximate solutions are not able to find all errors in the partial implementation, but they are correct in the sense that they do not report an error if there is still a possibility to implement the Black Boxes leading to a correct overall implementation. ...
... Then we successively increase the exactness (and the complexity) of the algorithm resulting in a local check (Sec. 2 In particular, in Section 2.2.3 we give an exact criterion to decide for a given partial implementation and a specification whether the partial implementation is correct or not. Unlike previous approaches [10,9] we can guarantee that there is really an extension of the partial implementation to a correct complete implementation, if the criterion of Section 2.2.3 reports no error (and of course, vice versa, there is no extension of the partial implementation to a complete implementation, if it does report an error). ...
We consider the problem of checking whether a partial implementation can (still) beextended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented:Starting with a simple 0,1,X-based simulation, which allows approximate solutions, but is not able to find all errors in the partial implementation, we consider more and more exactmethods finally covering all errors detectable in the partial implementation. The exact algorithm reports no error if and only if the current partial implementation conforms tothe specification, i.e. it can be extended to a full implementation which is equivalent to the specification.We give a series of experimental results demonstrating the effectiveness and feasibility of the methods presented.
... The present paper deals with algorithms for equivalence checking of partial implementations under the assumption that a combinational circuit is given as specification and also all implementations and Black Boxes are of combinational nature. First methods to handle this problem have been proposed in [10,9]. While these papers provide algorithms to find errors, it is not clear which errors and how many of the potential errors are detected. ...
... Our algorithms need different amounts of resources (space and time) and differ from their accurateness: They range from a simple algorithm using symbolic simulation for an approximation of the solution to an exact solution of the problem. Thereby the methods given in [10,9] are classified too. Approximate solutions are not able to find all errors in the partial implementation, but they are correct in the sense that they do not report an error if there is still a possibility to implement the Black Boxes leading to a correct overall implementation. ...
... Then we successively increase the exactness (and the complexity) of the algorithm resulting in a local check (Sec. 2 In particular, in Section 2.2.3 we give an exact criterion to decide for a given partial implementation and a specification whether the partial implementation is correct or not. Unlike previous approaches [10,9] we can guarantee that there is really an extension of the partial implementation to a correct complete implementation, if the criterion of Section 2.2.3 reports no error (and of course, vice versa, there is no extension of the partial implementation to a complete implementation, if it does report an error). ...
We consider the problem of checking whether a partial implementation can (still) be extended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented: starting with a simple 0,1,X-based simulation, which allows approximate solutions, but is not able to find all errors in the partial implementation, we consider more and more exact methods finally covering all errors detectable in the partial implementation. The exact algorithm reports no error if and only if the current partial implementation conforms to the specification, i.e. it can be extended to a full implementation which is equivalent to the specification. We give a series of experimental results demonstrating the effectiveness and feasibility of the methods presented.
