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The continuing improvement of processor performance has increased the demand on interconnection bandwidth at a rate that outpaces the bandwidth provided by conventional electrical interconnects. By combining a high-bandwidth optical interconnect technology with the ubiquitous high-performance CMOS technology, optoelectronic routers show the potenti...
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... interconnection network is the communication backbone of a parallel processor system on which all remote data accesses occur and, thus, has a strong influence on the overall performance of the system. While the bandwidth delivered by conventional electronic-based networks has increased slowly in recent years, the bandwidth demanded by processors has increased at a much faster pace, soon causing the network to become a performance bottleneck. Optoelectronic-based networks can potentially provide much higher bandwidth capacity to mitigate this problem [1, 2]. However, with the present growth rate of communication demand of distributed multiprocessor systems, even a high- bandwidth optoelectronic network (see figure 1), could become oversaturated unless advanced routing techniques are incorporated in the interconnect architecture to efficiently utilize the bandwidth. In this paper, we evaluate the design trade-offs and present architecture and operation of the WARRP II router chip (wormhole adaptive recovery-based routing via pre- emption). The router supports true fully adaptive routing that allows packets to use any profitable path through the network without restrictions. Network traffic can thus be evenly distributed throughout the links, achieving maximum bandwidth utilization. The router employs novel mechanisms to handle network deadlocks—hold-and-wait situations where no packet can make progress due to cyclic dependences on network resources. Although previous work has indicated that deadlocks can occur infrequently [3], they must be guarded against to ensure proper network operation. The WARRP II router handles impending deadlocks by progressively recovering from them. Each router uses a centralized deadlock buffer , shared among its neighbours, to perform a deadlock recovery operation through what is essentially a deadlock recovery path used to route a potentially deadlocked packet. On the optoelectronic side, the WARRP II router explores a critical design space that integrates large and complex circuitry with a dense array of optoelectronic devices. Although this is integral to the development of high- performance optoelectronic processors, memories, switches and network interfaces, it has not been heavily ...
Citations
This chapter presents a brief overview of some of the major research contributions in the area of VLSI computing with optical
interconnects from the early modelings of the 1980s to today’s MEMS implementations. Both free-space and fiber-guided interconnects are
covered. Various models and architectures with optical interconnects are shown, and aspects of their algorithmic design are
also reviewed. The chapter concludes with a brief discussion of some of the current advancements in MEMS and nanotechnology
that could pave the way towards the actual implementation of some of the theoretical models that were proposed in the 1980s,
and eventually towards designing of all optical systems. The materials presented in this chapter are compiled from some of
the references that are listed chronologically at the end of the chapter.
