Figure 6 - available via license: Creative Commons Attribution 3.0 Unported
Content may be subject to copyright.
Source publication
Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount of energy saved by a scratchpad memory....
Context in source publication
Context 1
... WIMS microcontroller has been implemented in both 180-and 65-nm processes [2,29], as depicted in Figures 6 and 7, with a small scratchpad memory to augment the on-chip main memory banks. Because it has had relatively few architectural changes between generations, it is a good test bed for evaluating the advantages of scratchpad memories as processes are scaled. ...
Citations
... The explicit control of data provides the much needed time predictability [7] and facilitates the static analysis process to obtain a safe and tight upper bound for the WCET [4] of a program. Moreover, replacing caches with SPMs can save the die area and reduce per access power consumption [6], [8]. ...
... where sz f denote the stack frame size of function f and SPMSIZE is the size of the SPM. According to Equation (8), stack size at node v (S v ), is equal to the stack frame size of function fn(v) if the stack of caller was evicted before (management operations are inserted) and it is equal to the summation of previous stack and the stack size of fn(v), if the caller's stack remains in the SPM. Note that, Equation (9) ensures that the stack size is always smaller than the size of the SPM. ...
... Note that, Equation (9) ensures that the stack size is always smaller than the size of the SPM. Equation (8) needs to be linearized similarly as in Equation (6). When a solver finds the optimal solution for the above ILP, we can find an optimal set of call sites from M v variables. ...
In systems with strict timing requirements, worst-case execution times (WCETs) are of utmost importance since missing a deadline can cause a failure. Cache memories are promising for average-case performance but have a great impact on the pessimism of WCET. Compared to caches, scratchpad memories (SPMs) provide a time-predictable alternative that requires explicit management in the software. Since a large number of accesses to the memory are to stack data [1], by keeping the call stack in the SPM instead of main memory, many of accesses to the memory can benefit from the time-predictable characteristics of the SPM and therefore, result in a tight WCET. The size of the SPM, however, is limited, and stack frames may need to be evicted to and restored from the main memory to avoid stack overflow. In this paper, we propose a technique to find optimal locations in a given program to perform stack management operations such that the WCET of the program is minimized. Compared to the closest related work, our technique is able to reduce the WCET up to 48% in the evaluation with several benchmarks from Mälardalen WCET suite. Additionally, results indicate that our technique can achieve up to 49% lower WCET compared to 2-way set associate caches.
Hardware/Software Codesign (HSCD) is an integral part of modern Electronic System Level (ESL) design flows. This chapter will review important aspects of hardware/software codesign flows, summarize the historical evolution of codesign techniques, and subsequently summarize each of its major branches of research and achievements that later will be presented in detail by different parts of this Handbook of Hardware/Software Codesign.
