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![A conceptual view of a 3D IC chip, with a through-silicon-via (TSV) used as interconnect between two dies or wafers [6].](profile/Fawnizu-Azmadi-Hussin/publication/224238954/figure/fig1/AS:302855434063876@1449217770839/A-conceptual-view-of-a-3D-IC-chip-with-a-through-silicon-via-TSV-used-as-interconnect.png)
A conceptual view of a 3D IC chip, with a through-silicon-via (TSV) used as interconnect between two dies or wafers [6].
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This paper investigates the challenges of a 3D-stacked system-on-chip testing, especially in terms of thermal problem. It is known that test power can be more than twice the intended power dissipation of the chip in the functional mode, for a single die. This problem is exacerbated when more than one dies are stacked on top of each other in a singl...
Context in source publication
Context 1
... the last three years, several research papers have been presented on the test of through-silicon-via (TSV)-based 3D stacked IC (SIC) chips. 3D SIC chips are either TSV-based ( Figure 1) or based on flip-chip technology, where each die layer is fabricated independently and the inter-die interface go through the I/O pads and wire bonds. In this work, both types of 3D chips are applicable. ...
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Citations
... A detailed comparison is made with Chandran et al. [7] and Wu et al. [8]. However, we do not compare our results with Fawnizu et al. [26] and Indira et al. [27], since their work is entirely based on SIC not on SoC. Further, they had proposed scheduling on the basis of temperature constraint but not with the objective of reducing test time like us. ...
The technology of 3D-ICs has been widely used in designing core-based systems-on-chip (SoC), which comprises vertical stacking of multiple silicon and metal layers, interconnected using through-silicon vias (TSV). Testing of the embedded cores in such a device not only requires a specially designed test access mechanism (TAM) but proper scheduling of tests in order to minimize the overall test time. Because of the design constraints on the number of TSVs (TSV count), the accessibility to different layers is often compromised, leading to an increase in test time. Also, the energy consumed during the execution of tests mandates the deployment of thermal vias to facilitate heat dissipation from various layers. In this manuscript, a scheduling-based test time reduction scheme for post-bond testing of 3D SoCs is proposed, which aims to reduce the test time under the constraints on TAM width, TSV count, and power budget. We address this problem by proposing a new partitioning method for assigning the layers to cores satisfying these optimization criteria. The proposed method has been tested on several ITC-02 benchmarks, and results show a notable reduction in test time for most of the cases compared to previous work.
... Our work is based on finding the temperature of individual cores which constitute a single stack. We have built up a 3D-SoC by stacking several layers of SoC d695 [18]. The d695 consists of 10 cores. ...
... In order to test the dies and the relative cores, a test access mechanism (TAM) is needed to transport test data to the cores on the dies. In general, we also need a 3D TAM [21][22][23][24][25] to transport test data from the stack input/output port on the bottom. As we design the test architecture, we should consider not only minimizing the test length, but also minimizing the number of TSV used to route 3D TAM and the number of stack test pins. ...
A new meta-heuristic method is proposed to enhance current meta-heuristic methods for global optimization and test scheduling for three-dimensional (3D) stacked system-on-chip (SoC) by hybridizing grey wolf optimization with differential evolution (HGWO). Because basic grey wolf optimization (GWO) is easy to fall into stagnation when it carries out the operation of attacking prey, and differential evolution (DE) is integrated into GWO to update the previous best position of grey wolf Alpha, Beta and Delta, in order to force GWO to jump out of the stagnation with DE's strong searching ability. The proposed algorithm can accelerate the convergence speed of GWO and improve its performance. Twenty-three well-known benchmark functions and an NP hard problem of test scheduling for 3D SoC are employed to verify the performance of the proposed algorithm. Experimental results show the superior performance of the proposed algorithm for exploiting the optimum and it has advantages in terms of exploration.
The semiconductor industry is always looking for some new technology in order to house the ever increasing number of devices in as small area as possible. One such solution is offered by the three dimensional SoCs which is vertical stacking of the various dies. It also has associated with it various challenges and constraints which need to be overcome before its adoption. Power density is also increasing, resuling in increased heat as more and more functions are being realised in a single chip. Cooling methods have to be adopted. Again testing results in more heat generation than functional mode of the chip. In this paper we have tried to analyze the effect of floorplanning on the maximum temperature. The benchmark circuit d695 has been taken and difference of temperature between various floorplans has been obtained. It shows here that the difference in temperature can be as high as 38K for a modified floorplan compared to original one.
Increasing design complexity coupled with new design and manufacturing techniques being used for modern integrate circuits is creating challenges for test environment. The goal of system-on chip (SoC) test scheduling has always been to reduce test application time. Added design constraints for SoC environment are making this scheduling more difficult. This difficulty is increased by manufacturing techniques like 3D stacked integrated circuits. Traditional test schedules for 3D stacked ICs can be either prohibitively long or may not exist without resorting to test partitioning. Partitioning methods proposed in literature have been ad hoc or simplistic. This paper presents a test partitioning method specifically designed for thermally constrained tests for the purpose of reducing test application time of 3D stacked integrated circuits under temperature constraint. The efficiency of the method is demonstrated by comparing it to the ad hoc methods previously investigated in the literature.
With technology scaling towards smaller geometries, the power density of modern integrated circuits (ICs) can potentially result into high temperatures during test, a problem further compounded by stacking dies in 3D stacked structures (3DSICs). Scheduling tests in a way to minimize the total test time becomes a key issue when temperature constraints are involved, since a more compact schedule leads to a hotter device. Unfortunately, many previous attempts at temperature-bounded scheduling either use inferior temperature models leading to under compaction, or they can only be applied to traditional single-die designs. Simple thermal models based on steady state temperatures are inadequate to schedule tests in 3DSICs due to their limitations. This paper proposes two formulations for test scheduling under thermal constraints for 3DSICs using the superposition principle, which allows for accurate thermal modeling and superior test compaction. This paper then compares them to previous formulations which use steady-state models, and also discusses the inherent limitations of the steady-state model. Results of the algorithms proposed in this paper show the superiority of the schedules obtained for testing 3DSICs.
A lot of present research is being devoted to the adoption of a new technology called 3D integration. The demand of today is also to enable the heterogeneous integration of different technologies so that a true SoC design can be realised. The technology poses several problems, the prominent ones being the removal of heat. The testing issue also comes into picture. One of the possible solutions to the problems can be the spliting of the inner stacks into more than one group and testing of these first so as to take advantage of low ambient temperature in the beginning of testing. The floorplan has been adjusted and the effect on temperature studied.
