A complete four-stage delay block (extendable to eight stages). 

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... shown in Fig. 1(b), a TR-receiver can support self-synchronizing demodulation because it does not need a separate template signal for the RF correlator (mixer) in its front-end. But to realize this feature, it will require a delayed version of the received pulse-train through a wideband delay-block (DB). This delay-block should be able to handle high data rate of reference pulses and regulate them in a controlled manner. Design criteria warrant compatibility of the delay-block with different amplifier topologies as it is placed between a low noise amplifier and a radio-frequency mixer in the receiver chain. Usage of variable delay units have been reported in applications ranging from voltage controlled oscillators (VCO) to pulse width control systems (PWCL) [20]. But a wideband delay- block for a TR-receiver demands special focus on minimizing power dissipation as the system needs to keep the average power density to the lowest permissible level [21]. Moreover, these delay -10 elements require wideband characteristics to be able to handle pulses with a duration of 10 s. The proposed architecture of a divided wideband delay-block (DB) built with 90 nm transistors and capable of processing bipolar message carrying pulses [22] is presented in Fig. 3. At its input port, the delay-block has an optional three-coil signal conversion block (L , L , and L ) to generate separate excitations for its top and bottom branches (at nodes b and c ). No loss in strength of the input feed is assumed in the conversion process (ideal coupling). The bottom feed is added with a bias voltage (V dd =1.2 V) through a resistive summer to generate an elevated pulse train (at node d ). To drive the delay-block and verify its delay regulation, an 800 mV test signal is applied to the proposed architecture. The strength of these test pulses can be tuned by adjusting the gain granted by the preceding amplifier. The primary objective of using two parallel sections in the circuit is to ensure uniform delay for all member pulses in the driving stream and power the delay block with a single bias rail (V rail ). For a single-stage DB, as shown in Fig. 3, the sectional delay chains (stage top.1 and stage bot.1 ) are built with a pair of cascaded inverter blocks and two intermediate capacitors. The unit stage top.1 is formed with devices T up.1 (14μ/0.1μ), T up.3 (1μ/0.1μ), T up.2/4 (16 μ/0.1μ) and drain-source shorted transistors contributing junction capacitance (C int.1=2 , in the range of 100 fF ). The driving stream for the bottom unit (stage bot.1 ) has a base voltage offset of 0.6 V and a different peak-to-peak coverage. As a result, it uses transistors with adjusted dimensions {T bot.1 (20μ/0.1μ), T bot.3 (8μ/0.1μ), T bot.2/4 (16 /0.1 )} and 50 fF shunt capacitors (C int.3/4 ). Output from these parallel units (at points x and y ) produces nearly uniform delays for bipolar pulses (average of 180 ps for a single block). In order to process negative pulses, the driving stream base was elevated to the 0.6 V range at the start of the bottom unit. As a result, a dc component of 1.0 V is present in the delayed signal at node y of stage bot.1 . This element is removed by an RC branch (made of R f.1 and C f.1 ) and the pulse base is brought back to near ground level. R add.3 and R add.4 form a second resistive summer which combines the sectional responses to generate a complete delayed pulse train at node z with relatively small signal dispersion. The overall delay achieved by the proposed single-stage DB is not fixated at 180 ps but can be fine tuned with a number of design parameters [22], as will be explained in the following sections. The branched architecture of the delay-block allows extension of numbe r of stages in each section (up to eight) during the testing process. Fig. 4 presents a four-stage wideband delay-block where eight delay units (stage and stage ) are divided between two sections/branches of the design. The device sizes (mentioned in the figure) remain consistent for the top section but need to be adjusted to deal with base elevated pulses in the bottom section. The progress of the delayed pulses at the intermediate nodes (m i and n j with { i, j }=1-4) is shown in the diagram which indicates a regular and monotonic variation of achieved delay. The four-stage DB introduces an average overall delay of ~420 ps and the difference in temporal positions of the negative pulse (t 2 +450 ps at node w and t 2 +420 ps at point z ) can be attributed to the resistive summation process. By controlling gain provided by the amplifier preceding the delay-block, the strength of input pulses and magnitude of dc offset needed in the bottom section can be predesigned. Since the wideband pulses are essentially regenerated in this scheme, no matching circuit will be needed for the delay-block as in the cases of LNA and RF mixer in the receiver chain. Further discussion on tuning and regulation of the proposed delay-block is documented in the result section. The expression for propagation delay achieved by the complete delay chain indicates a non-linear relationship between overall delay and number of stages or individual delay units in top and bottom sections. The pair of cascaded inverters in a single-stage branch, as shown in Fig. 3, controls the component delay with rail voltage (V rail ), shunt reactance (C int ), and device dimensions (W/L ratio) working as design parameters. For a single inverter gate, the value of saturation current flowing through the transistors (I ) is considered as average bias tree current and approximated by where the device (pull-down) threshold level is designated as V th.n and G n is transistor transconductance gain. A mirror equation obtained for the pull-up device will produce the same magnitude for the bias current. If strength of input pulses and voltage of bias rail are regulated in the circuit then the following relationship can also be maintained After we define t del.high.low and t del.low.high as propagation delays for the signal during high-to-low or low- to-high transition at inverter output and C shunt as intermediate shunt capacitance, unit inverter-delay for a delay gate can be derived as [23] If R eq.p and R eq.n represent equivalent resistances when pull-up and pull-down transistors are ’on’, FET signal transition times will be proportional to time constant of RC networks formed by device (which is on) resistance and shunt (load) capacitors. When signal drops from high to low at inverter output, the reactive network is realized with R eq.n and output capacitance C shunt . On the other hand, R eq.p becomes part of this RC circuit in case of low to high transition at gate output. Therefore, propagation delays can be defined with the ...

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... presented in Fig. 7(b), B 1f is found to have a magnitude between 0.524 and 0.97 in the concerned range of bandwidth (18.1-24.3 GHz). To verify this result with a second stability parameter, the Rollett stability factor (K rollet ) is also plotted in the same figure with its value always being greater than a unit limit (fulfilling its criterion of stability) [13]. This factor is also defined with s-parameters and has a relatively flat profile (3.71-3.82) with a lowest trough of 3.707 at 21.6 GHz. As a result, the amplifier will provide resistance to oscillation induced by white noise which may get accumulated in the circuit during its start-up mechanism. The proposed wideband delay-block (DB) to follow the front-end amplifier is also built with 90 nm CMOS devices as a part of the TR-receiver architecture. To illustrate the progression of a driving bipolar pulse stream through a multi-stage delay chain, a six-stage delay-block (built with the same principle presented in Fig. 4) is subjected to a pulse train of monocycle gaussian pulses. Fig. 8(a) presents the time domain signals existing at different nodes of the top section for a complete six-stage DB. Delayed versions (130-500 ps) of the positive half of the input pulse are collected from output nodes ( m 1 -m 6 ) of six successive stages (See Fig. 4) and a sample intermediate node ( i 1 ) in the first stage of the delay chain. A symmetric balun produces identical replicas of the the driving pulse and feed them as sectional inputs (at points b and c). In Fig. 8(b), after the input pulse is elevated with a bias voltage (V dd ) for the bottom section, the driving signal is now collected from point d. Delayed versions for the elevated negative-half of the input signal show a progression of 150-650 ps at output nodes of stages in the bottom section ( n 1 -n 6 ). The final response (at node y ) gathered after six stages in the bottom section is decoupled (dc component removed) at node w as shown in Fig. 8(c). It also shows the signal produced by the output combiner (culminating at node z ) which manifests an average delay of 620 ps. Similar number of stages are employed in the DB branches to achieve identical and uniform delay for all pulse elements. The responses demonstrate that monotonic and quasi-linear rise in delay is available at output node of each of the six stages. To measure this phenomenon, (W/L) p.(up/bot).q is selected as the notation to define dimension of individual transistors and C p.int.q expresses value of a shunt DB capacitor where p=1-6 are stage indices of delay sections and q=1-4 indicate individual transistors or capacitors for a particular stage. To produce the response in Fig. 8, V is set to 0.95 V and dimensions of the first stage are selected as The other five stages require manipulation of device dimensions to compensate for any signal drop at intermediate nodes. Power dissipated by a single-stage delay-block is kept below 9 mW and for a six- stage delay unit power penalty reaches up to 10.6 mW. According to design requirement, number of stages in the DB can be varied to achieve regulated temporal shifts. The signal typically collected by a TR-receiver front-end is shown in Fig. 9(a) in the form of a wideband pulse stream made with monocycle gaussian pulses. Fig. 9(b) presents its delayed versions collected from the output ports of the proposed multi-stage delay-block. In addition to the number of stages in a DB section, tuning of delay may also be controlled by shunt capacitors, ratio of transistors, and magnitude of rail voltage [22]. This phenomenon is further illustrated in tabular form for a single-stage delay-block in the following ...

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... presented in Fig. 7(b), B 1f is found to have a magnitude between 0.524 and 0.97 in the concerned range of bandwidth (18.1-24.3 GHz). To verify this result with a second stability parameter, the Rollett stability factor (K rollet ) is also plotted in the same figure with its value always being greater than a unit limit (fulfilling its criterion of stability) [13]. This factor is also defined with s-parameters and has a relatively flat profile (3.71-3.82) with a lowest trough of 3.707 at 21.6 GHz. As a result, the amplifier will provide resistance to oscillation induced by white noise which may get accumulated in the circuit during its start-up mechanism. The proposed wideband delay-block (DB) to follow the front-end amplifier is also built with 90 nm CMOS devices as a part of the TR-receiver architecture. To illustrate the progression of a driving bipolar pulse stream through a multi-stage delay chain, a six-stage delay-block (built with the same principle presented in Fig. 4) is subjected to a pulse train of monocycle gaussian pulses. Fig. 8(a) presents the time domain signals existing at different nodes of the top section for a complete six-stage DB. Delayed versions (130-500 ps) of the positive half of the input pulse are collected from output nodes ( m 1 -m 6 ) of six successive stages (See Fig. 4) and a sample intermediate node ( i 1 ) in the first stage of the delay chain. A symmetric balun produces identical replicas of the the driving pulse and feed them as sectional inputs (at points b and c). In Fig. 8(b), after the input pulse is elevated with a bias voltage (V dd ) for the bottom section, the driving signal is now collected from point d. Delayed versions for the elevated negative-half of the input signal show a progression of 150-650 ps at output nodes of stages in the bottom section ( n 1 -n 6 ). The final response (at node y ) gathered after six stages in the bottom section is decoupled (dc component removed) at node w as shown in Fig. 8(c). It also shows the signal produced by the output combiner (culminating at node z ) which manifests an average delay of 620 ps. Similar number of stages are employed in the DB branches to achieve identical and uniform delay for all pulse elements. The responses demonstrate that monotonic and quasi-linear rise in delay is available at output node of each of the six stages. To measure this phenomenon, (W/L) p.(up/bot).q is selected as the notation to define dimension of individual transistors and C p.int.q expresses value of a shunt DB capacitor where p=1-6 are stage indices of delay sections and q=1-4 indicate individual transistors or capacitors for a particular stage. To produce the response in Fig. 8, V is set to 0.95 V and dimensions of the first stage are selected as The other five stages require manipulation of device dimensions to compensate for any signal drop at intermediate nodes. Power dissipated by a single-stage delay-block is kept below 9 mW and for a six- stage delay unit power penalty reaches up to 10.6 mW. According to design requirement, number of stages in the DB can be varied to achieve regulated temporal shifts. The signal typically collected by a TR-receiver front-end is shown in Fig. 9(a) in the form of a wideband pulse stream made with monocycle gaussian pulses. Fig. 9(b) presents its delayed versions collected from the output ports of the proposed multi-stage delay-block. In addition to the number of stages in a DB section, tuning of delay may also be controlled by shunt capacitors, ratio of transistors, and magnitude of rail voltage [22]. This phenomenon is further illustrated in tabular form for a single-stage delay-block in the following ...