Figure - available from: Analog Integrated Circuits and Signal Processing
This content is subject to copyright. Terms and conditions apply.
A complementary differential pair with resistors connected at the output, four capacitors at the input to decouple the input voltage, and a simple output CMFB

A complementary differential pair with resistors connected at the output, four capacitors at the input to decouple the input voltage, and a simple output CMFB

Source publication
Article
Full-text available
Noise Efficiency Factor (NEF) is the most employed figure of merit to compare different low-noise biomedical signal amplifiers, taking into account current consumption, noise, or bandwidth trade-offs. A small NEF means a more efficient amplifier, and was assumed to be always NEF > 1 (an ideally efficient single BJT amplifier). In this work current-...

Similar publications

Article
Full-text available
A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18 μ m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efficiency >70% for load currents in the ra...
Article
Full-text available
This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing techni...

Citations

Article
This paper presents a fully self-biased, low-power LNA for neural recordings. Due to the capacitor coupling and low-supply voltage in LNA, the appropriate dc bias voltages for saturating the input transistors NMOS and PMOS of LNA should be separately provided. This paper focuses on the effects of different feedback ways to obtain input dc bias voltage, and proposes a completely self-biased structure to obtain the bias voltage directly from the inner nodes of the circuit. This connected way avoids using extra dc biasing circuit totally, saves capacitor area effectively and reduces the high-pass corner frequency greatly. Furthermore, the proposed method eliminates the likelihood for initial DC latch-up in the traditional way, making the circuit more stable. Simulated in a 0.18-µm CMOS process, the LNA consumes 1.2 µA from a 0.6 V supply, and achieves an input referred noise of 4.98 µVrms (1–10 kHz), corresponding to a noise efficiency factor of 2.13. Simulated CMRR and THD exceed 77 dB and 75 dB, separately.