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A class A npn BJT RF amplifier with collector feedback: small signal AC test circuit and example gain and phase response curves; legend: solid line = dB(Vout.v/Vin.v) the amplifier gain in dB and dotted line = wphase(Vout.v/Vin.v) the unwrapped phase of the amplifier gain in degrees.
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... "inout" terminals given in the Verilog-A module statement. The software also attaches a list of device parameter properties to the C++ compiled model icon associated with the new model. Fig. 3. Verilog-A code for a simplified RF npn BJT model: the model parameters have the same meaning as those defined in the SPICE 3f5 BJT model [12]. Shown in Fig. 4 is a single stage, class A, RF npn BJT amplifier circuit, with collector feedback, configured for small signal AC simulation over the frequency band 1MHz to ...
Citations
... As one can see, the most accurate results (compared with the numerical ones) are obtained in the case of the GL-fit factor ε GL . Equation (2) with Eq. (6) for the smoothing factor was implemented in a Verilog A compact model code and simulated in QucsStudio simulator [13,14]. The simulated output characteristics for MOSFET A are shown in the right plot in Fig. 4. ...
An improved surface-potential-based metal–oxide–semiconductor field-effect transistor (MOSFET) model is presented. The improvement consists in introducing a new generalized logistic functional form for the smoothing factor that allows for a continuous transition of the surface potential from the depletion to strong inversion region. This functional form takes into account specific changes in the technological characteristics of MOSFET devices. The model combines the advantages of both regional and single-piece models and satisfies all requirements for compact models, i.e., continuity, accuracy, scalability, and simulation performance. Comparison with numerical data shows that the model provides an accurate description of the surface potential for a wide range of substrate doping and oxide thickness.
... Such a functionality is available in a number of EDA tools which have been equipped with interfaces enabling running Verilog-A models. Further progress in this field has been reported in [9,10]. In the Qucs, QucsStudio programs the software not only undertakes automatic synthesis of the C++ code based on Verilog-A, but also dynamically links it with the circuit simulator program core. ...
... On the other side there are nice Free and Open-Source Software (FOSS) solutions, e.g. [9, 20, 21], or freely available but not open-source ones [22], which provide access to the complete state-of-the art compact models, ready for use for technology characterization and circuit design in research laboratories. Developing a software for the model parameter extraction becomes an important task. ...
A GNU Octave - based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I–V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I–V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I–V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV © . Selected aspects of the application are presented and discussed.
... Although Qucs and QucsStudio have a similar structure and function the XML scripts provided with each package are different reflecting the underlying structure of the circuit simulator adopted by their developers, for example Qucs uses static code libraries and QucsStudio dynamic linked code libraries. Further details of the Qucs and Qucstudio approaches to compact device modelling using Verilog-A can be found in the following references [15] [16]. However, it is worth noting that the C++ compact models built with either Qucs or QucsStudio and ADMS 2.30 work in all simulation domains, specifically DC, small signal AC (including noise analysis), Transient, S parameter small signal AC (including noise analysis) and Harmonic Balance Simulation. ...
SUMMARYMOS-Modelle und Parameterextraktion Arbeitskreis (MOS-AK) is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling enthusiasts to promote advanced compact modelling techniques and model standardization using high-level behavioural modelling languages such as VHDL-AMS and Verilog-A. This invited paper summarizes recent MOS-AK open-source compact model standardization activities and presents advanced topics in metal–oxide–semiconductor field-effect transistor modelling, focusing in particular on analogue/radio frequency applications. The paper discusses links between compact models and design methodologies, finally introducing elements of compact model standardization. The open-source computer-aided design tools Qucs, QucsStudio and ngspice all support Verilog-A as a hardware description language for compact model standardization. Latter sections of this paper describe a Verilog-A implementation of the EKV3 MOS transistor model. Additionally, the simulated radio frequency model performance is evaluated and compared with experimental results for 90 nm CMOS technology. Copyright © 2014 John Wiley & Sons, Ltd.
The rapid expansion in emerging semiconductor devices has led to the need for improved
compact modelling and circuit simulation tools. In order to achieve wide spread acceptance of any new modelling tool it must be simple to use, generate device models that produce accurate simulation data, simulate at practical speeds, meet international hardware description language standards and be freely available to the compact modelling community. This presentation reports on current research that links
Equation-Defined Device modelling with Verilog-A modules, driven by code templates and synthesis, which in turn result in an improved interactive modelling technique that can be employed to construct compact models that have a similar performance to compiled C++ code models. Throughout the talk a series of compact device models will be introduced to demonstrate the fundamentals and application of the new approach to compact device modelling.
The purpose of this presentation is provide an overview of the fundamentals of the Verilog-A hardware description language and its use in compact modelling of established and emerging semiconductor technology devices. With the adoption of Verilog-A as the standardised model interchange language by CMC, a knowledge of this subject is of increasing importance to the modelling community. Similarly, access to freely available Verilog-A modelling tools and circuit simulators is essential if Verilog-A modelling techniques are to be widely adopted. For this reason, in an attempt to encouraging all who attend to experiment with Verilog-A. the presentation is based on the Qucs-S, QucsStudio and the MAPP/Octave FOSS software. Throughout the talk a series of modelling case studies outline the stages in the development of Verilog-A models for established and SiC semiconductor devices. In the later stages of the presentation participants are also introduced to using the Berkeley MAPP tools with Qucs-S/Xyce.
In the paper a simple compact model of a transfer of a mechanical energy into an electrical energy is presented. The mechanical energy is stored in a vibrating bimetallic membrane with an electret layer. The membrane vibrations are forced by a set-up consisting of a cold and hot surfaces. During the vibrations this set-up acts as a variable capacitor with one of the electrodes being constantly charged. The charge stored on the other plate of this capacitor varies periodically and is transferred to the external storage capacitor via a simple Graetz circuit. Acompact model of this mechanism has been derived and implemented in an open-source Quite Universal Circuit Simulator (Qucs) program as a circuit including a specific Equation-Defined Device component. The simulation data have been compared with experimental ones, demonstrating promising features of the proposed approach.
Qucs-0.0.18: Structure and basic modelling features; Qucs-0.0.19: Introducing the next generation Qucs simulation and modelling tools; Qucs circuit simulation and device modelling: Simulation, subcircuits, post-simulation data processing, algebraic equation-defined components and embedded design routines. Compact device modelling: 1. Equation-Defined Device models (EDD), Radio Frequency and Equation-Defined Models (FEDD); 2. Analogue Device Model Synthesis (ADMS) of Verilog-A behavioural and lower level device and circuit models, Qucs ADMS/Verilog-A “turn-key” tools; 3. Expanded compact device modelling capabilities with the Berkeley Model and Algorithm Prototyping Platform (MAPP); 4. A unified GPL compact device modelling and simulation platform.
